Methods and devices for bypassing the internal cache of an advanced DRAM memory controller
AssigneeUpmem
InventorsJean-François Roy, Fabrice Devaux
Life of this patent
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Abstract
A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.
Claims17
A calculation system comprising
- a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory;
- and
- a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the computing device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses, wherein each address of the plurality of first addresses includes a first n-bit value and a second p-bit value, the computing device being configured to perform a writing operation of writing data to the m bits of the first memory location by performing a reading operation of the first memory location using one of the first addresses having a first selected n-bit value and a second p-bit value generated according to the writing data.
A method for accessing a memory circuit coupled to the memory controller of a computing device via a data bus and an address bus, the computing device having one or several core processors and the memory controller comprising a cache memory, the process including:
- selecting, by the computing device, for each memory operation accessing a first m-bit memory location of the memory circuit, an address among a plurality of first addresses, the first m-bit memory location being accessible by each of the plurality of first addresses provided on the address bus, wherein each address of the plurality of first addresses includes a first n-bit value and a second p-bit value, the computing device being configured to perform a writing operation of writing data to the m bits of the first memory location by performing a reading operation of the first memory location using one of the first addresses having a first selected n-bit value and a second p-bit value generated according to the writing data.
Dependencies are inferred from the claim text.