Method and circuit for protecting a DRAM memory device from the row hammer effect

A method of protecting a DRAM memory device from a row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one prevention logic configured to respectively define sub-banks as contiguous sections of rows of a bank, each sub-bank being associated with an activation threshold, and to execute, at each activation of a row of a given sub-bank of the sub-banks of the memory device, a step of incrementing an activation counter associated with the given sub-bank and determination of a required number of preventive refreshes of this of the given sub-bank;

• the prevention logic also being configured to execute a preventive refresh sequence comprising:
• a step of identifying a need for preventive refresh of a determined sub-bank of the sub-banks of the memory device based on one or more characteristics related to the sub-banks;
• a step of triggering an operation to refresh a current index row associated with the determined sub-bank;
• a step of incrementing the current index row associated with the determined sub-bank;
• decrementation of the required number of preventive refreshments of this of the determined sub-bank;
• wherein the operation to refresh the current index row is forming a step of a preventive refresh cycle leading to refresh at least all the rows of the determined sub-bank;
• and wherein the activation threshold of the determined sub-bank is chosen so that a complete preventive refresh cycle of the determined sub-bank is carried out before the number of rows activated in the determined sub-bank exceeds a critical hammer value.