Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering

A DRAM memory controller (1000), the controller being intended to configure a protection of DRAM memories against a memory row-hammering effect, the protection involving the implementation of a control circuit (1200) and a protection memory block (1101) having a predetermined capacity, the controller being adapted to:

• determine the total capacity of the DRAM memories controlled by the controller (1000);
• if the total capacity of the DRAM memories exceeds a size, referred to as the threshold size, beyond which the protection by an algorithm implementing a single table saved in the protection memory block (1101) is impossible, the controller (1000) divides the total capacity of the DRAM memories into N parts, N≥2, each part i, for i ranging from 1 to N, N and i being integer values, and configures the control circuit (1200) to execute N protection algorithms each referred to as algorithm i, for i ranging from 1 to N, each algorithm i being intended to protect the part i from the row-hammering effect by means of a table i, each table i, for i ranging from 2 to N, being saved in part i−1, while table 1 is saved in the protection memory block (1101), if the total capacity of the DRAM memories does not exceed the threshold size, the controller configures the control circuit (1200) so that it protects said DRAM memories by means of a single algorithm that implements a table stored in the protection memory block (1101).