Dram memory device using a mechanism for row hammer management
AssigneeUpmem
InventorFabrice Devaux
Life of this patent
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Abstract
The invention relates to a memory device that comprises: —a memory bank provided with n memory rows, each row i being liable to effect a row hammer having a range p; —a block for preventing the hammer effect which comprises counting means implementing m hammer counters, each counter k being associated with one or more of the rows i, and is configured to increment a count k by an increment value kN, the increment value kN being a decreasing function of the duration TPN and also a function of the duration TAN, the increment value kN quantifying the effect of the hammer from the one or more rows i on rows j within hammering range; —a row refresh block configured to refresh one or more rows as soon as a count k reaches a threshold value M.
Claims15
A DRAM memory device which comprises:
- at least one DRAM memory bank provided with n memory rows, referred to as row i for i ranging from 1 to n, each row i being liable to effect a row hammer having a range p on one or more rows j, said to be within the hammering range of row i, with j ranging from i+1 to i+p and from i−1 to i−p, each row i being configured to have activation cycles N imposed on it continuously, an activation cycle N comprising an activation AN, of duration TAN, and a preload PN, of duration TPN, preceding the activation AN;
- a logic block for preventing the hammer effect which comprises counting means implementing m hammer counters, called counters k, k ranging from 1 to m, each k counter being associated with one or more of the rows i, and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value kN, the increment value k being a decreasing function of the duration TPN and also a function of the duration TAN, the increment value kN quantifying the hammer effect from the one or more of the rows i on rows j within hammering range;
- a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M, the threshold value M being chosen to prevent the row hammer effect.
A method for preventing the memory row hammer effect of a DRAM device, the DRAM device comprising at least one DRAM memory bank provided with n memory rows called row i for i ranging from 1 to n, the method comprising the implementation of an algorithm for preventing the row hammer effect, said algorithm implementing:
- -m hammer counters, called counters k, k ranging from 1 to m, each k counter being associated with one or more of the rows i, and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value kN, the increment value kN being a decreasing function of the duration TPN and also a function of the duration TAN, the increment value kN quantifying the hammer effect from the one or more of the rows i on rows j within hammering range;
- a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M, the threshold value M being chosen to prevent the row hammer effect.
Dependencies are inferred from the claim text.