STMicroelectronics SDN BHD
Muar, MY· latest recorded location
STMicroelectronics SDN BHD is named on 7 US grants and 9 published applications in this corpus. Its most frequent classification is H10W (Generic packages, interconnections, connectors or other constructional details of devices covered by).
- Granted patents
- 7
- Published applications
- 9
- Inventors
- 11
- Granted in 2026 so far
- 0
- Most recent grant
- 30 Jan 2024
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2003 | 0 | 1 |
| 2004 | 1 | 0 |
| 2005 | 0 | 0 |
| 2006 | 1 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 1 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 1 |
| 2016 | 0 | 1 |
| 2017 | 1 | 0 |
| 2018 | 1 | 1 |
| 2019 | 0 | 0 |
| 2020 | 1 | 0 |
| 2021 | 0 | 1 |
| 2022 | 0 | 2 |
| 2023 | 0 | 0 |
| 2024 | 2 | 1 |
By publication year.
Technology areas
Share of 16 documents
Recent patents
- Method of producing semiconductor devices and corresponding semiconductor device30 Jan 2024US 11,887,921 B2
- Mold flow balancing for a matrix leadframe2 Jan 2024US 11,862,540 B2
- Integrated circuit device with plating on lead interconnection point and method of forming the device30 Jun 2020US 10,699,990 B2
- Integrated circuit device with plating on lead interconnection point and method of forming the device28 Aug 2018US 10,062,639 B2
- Rough leadframe with a nanolayer of silver13 Jun 2017US 9,679,832 B1
- Method of producing semiconductor devices and corresponding semiconductor device11 Apr 2024US 2024/0120267 A1
- Integrated circuit package with v-shaped notch creepage structure19 May 2022US 2022/0157681 A1
- Method of producing semiconductor devices and corresponding semiconductor device3 Mar 2022US 2022/0068788 A1
- Mold flow balancing for a matrix leadframe9 Sep 2021US 2021/0280502 A1
- Integrated Circuit Device with Plating on Lead Interconnection Point and Method of Forming the Device6 Dec 2018US 2018/0350728 A1
Most cited
By later US patents