Mircon Technology, Inc.
Boise, ID, US· latest recorded location
Mircon Technology, Inc. is named on 15 US grants and 6 published applications in this corpus. Its most frequent classification is G11C (Static stores).
- Granted patents
- 15
- Published applications
- 6
- Inventors
- 33
- Granted in 2026 so far
- 0
- Most recent grant
- 1 Aug 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 1 | 0 |
| 2004 | 1 | 1 |
| 2005 | 2 | 1 |
| 2006 | 0 | 1 |
| 2007 | 0 | 1 |
| 2008 | 3 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 1 | 0 |
| 2014 | 2 | 0 |
| 2015 | 1 | 0 |
| 2016 | 0 | 0 |
| 2017 | 1 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 1 |
| 2021 | 0 | 0 |
| 2022 | 1 | 1 |
| 2023 | 1 | 0 |
By publication year.
Technology areas
Share of 21 documents
- G11CStatic stores14
- G06FComputing and data processing6
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by5
- H10PGeneric processes or apparatus for the manufacture or treatment of devices covered3
- C11DDetergent compositions2
- G01RMeasuring electric variables2
- H03FAmplifiers2
- H03KPulse technique2
- H05KPrinted circuits2
- H10BElectronic memory devices2
Recent patents
- Predictive memory management1 Aug 2023US 11,714,558 B2
- Current monitor for a memory device22 Feb 2022US 11,257,534 B2
- Forming self-aligned conductive lines for resistive random access memories11 Jul 2017US 9,705,080 B2
- Programming based on controller performance requirements10 Feb 2015US 8,953,374 B2
- Command line output redirection27 May 2014US 8,739,122 B2
- Domain-based access in a memory device30 Jun 2022US 2022/0206718 A1
- Temperature compensation in a memory system5 Mar 2020US 2020/0073451 A1
- Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice22 Mar 2007US 2007/0063328 A1
- Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules28 Sep 2006US 2006/0215434 A1
- Differential input buffer for receiving signals relevant to low power15 Dec 2005US 2005/0276145 A1
Most cited
By later US patents
- Capture clock generator using master and slave delay locked loops43US 6,839,860 B22005
- Synchronized write data on a high speed memory bus37US 6,807,613 B12004
- Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor28US 5,849,624 A1998
- Technique for gated lateral bipolar transistors8US 6,638,807 B22003
- Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules6US 7,414,875 B22008