Synchronized write data on a high speed memory bus

A memory module comprising:

• at least one memory device, said memory device comprising:
• a write clock input path for receiving a write clock signal;
• a command signal path for receiving a write command;
• at least one data signal path for receiving write data;
• a data strobe signal path for receiving a write strobe signal which includes a first strobe portion, wherein said data strobe signal path is also used by said memory device to send a read strobe signal to a memory controller during a memory read operation;
• a logic circuit responsive to a write command on said command signal path and said first strobe portion of said write strobe signal for clocking in data received on said data signal path using a write clock signal received on said write clock input path;
• and
• a connector for electrically connecting said module to a signal bus.

A processor system comprising;

• a processor;
• and
• a memory device coupled to said processor, said memory device comprising:
• a write clock input path for receiving a write clock signal;
• a command signal path for receiving a write command;
• at least one data signal path for receiving write data;
• a data strobe signal path for receiving a write strobe signal which includes a first strobe portion, wherein said data strobe signal path is also used by said memory device to send a read strobe signal to a memory controller during a memory read operation;
• and
• a logic circuit responsive to a write command on said command signal path and said first strobe portion of said write strobe signal for clocking in data received on said data signal path using a write clock signal received on said write clock input path.

A memory device comprising:

• a write clock input path for receiving a write clock signal;
• a command signal path for receiving a write command;
• at least one data signal path for receiving write data;
• a data strobe signal path coupled to a strobe detector which senses a logical state of the data strobe signal path, said data strobe signal path having a first logical state corresponding to a first strobe portion and a second logical state corresponding to a second strobe portion;
• a logic circuit responsive to the write command and the strobe detector detecting the first logical state to start clocking in write data into a buffer using said write clock signal;
• wherein said logic circuit is responsive to the strobe detector detecting the second logical state to continue to clock in write data into the buffer and to count ticks of the write clock while the strobe detector detects the second logical state;
• and
• wherein said logic circuit is responsive to the strobe detector detecting the strobe signal at the first logical state to reset the buffer to discard previously clocked in data if the count is less than a first predetermined number.

A memory module comprising:

• a first command signal path for receiving a command;
• a first command clock signal path for receiving a command clock;
• a register coupled to the first command signal path and the first command clock signal path, wherein said register outputs the command received on the first command signal path to a second command signal path and outputs the command clock received on the first command clock signal path to a second command clock signal path;
• a write clock input path for receiving a write clock signal;
• a data signal path for receiving write data;
• a data strobe signal path for receiving a write strobe signal which includes a first portion;
• and
• at least one memory device, said memory device coupled to the second command signal path, the second command clock path, the write clock input path, the data signal path, and the data strobe signal path,
• wherein each of said memory device further comprises a logic circuit responsive to a write command on said second command signal path and said first strobe portion of said write strobe signal on said data strobe signal path for clocking in data received on said data signal path using a write clock signal received on said write clock input path.

A method of operating a memory device, said method comprising:

• receiving a write clock signal;
• receiving a write command;
• receiving a write strobe signal which has a first strobe portion associated with a clocking edge of said write clock signal, wherein said write strobe signal is received on a data strobe signal path of said memory device which is also used by said memory device to send a read strobe signal to the memory controller during a memory read operation;
• and
• clocking in write data using said write clock signal after receipt of said write command and beginning with the clocking edge associated with said first strobe portion.

A method of operating a memory device, said method comprising:

• initializing the memory device, said initializing further comprising:
• receiving a command clock signal;
• accepting a first write command in synchronism with a clock edge of the command clock signal;
• receiving a write clock signal;
• receiving a write strobe signal which has a first strobe portion associated with a clocking edge of said write clock signal, wherein said write strobe signal is received on a data strobe signal path of said memory device which is also used by said memory device to send a read strobe signal to the memory controller during a memory read operation;
• counting a number of write clock signals between the acceptance of the first write command and the first strobe portion of the write strobe signal.

A method of operating a memory device, said method comprising:

• receiving a write clock signal;
• receiving a write command and enabling a strobe detector, said strobe detector sensing a write strobe signal line which has a first logical state corresponding to a first portion of a strobe signal associated with a clocking edge of said write clock signal and a second logical state corresponding to a second portion of the write strobe signal;
• when the strobe detector senses the strobe signal at the first logical state, starting to clock in write data into a buffer using the write clock signal on the clocking edge associated with said first strobe portion;
• when the strobe detector sense the strobe signal at the second logical state, continuing to clock in write data using said write clock and counting the ticks of the write clock signal while the strobe signal is sensed at the second logical state;
• and
• when the strobe detector sense the strobe signal at the first logical state, resetting the buffer to discard previously clocked in data if the counting is less than a first predetermined number.