Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

A computer system, comprising:

• a central processing unit;
• a system memory;
• a bus bridge coupled to the central processing unit and the system memory and adapted to allow communication between the central processing unit and the system memory, wherein the system memory includes at least one memory module comprising:
• a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other;
• and
• at least one driver operatively coupled to at least one of the memory devices in a respective one of the memory ranks and to the bus bridge, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time.

A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

• providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated;
• receiving a plurality of command signals and a plurality of address signals into a plurality of driver chips via the bus;
• processing the plurality of command signals and plurality of address signals;
• and
• simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals.

A memory module having a memory interface, comprising:

• a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other;
• a driver sector electrically isolated from the at least two memory ranks;
• and
• at least one driver coupled to the driver sector and operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time.

A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

• providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated;
• receiving a plurality of command signals and a plurality of address signals via the bus;
• processing the plurality of command signals and plurality of address signals;
• and
• simultaneously writing to two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals.

A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

• providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated;
• receiving a plurality of command signals and a plurality of address signals via the bus;
• processing the plurality of command signals and plurality of address signals;
• and
• simultaneously reading from two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals.

A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

• providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated;
• receiving a plurality of command signals and a plurality of address signals via the bus, wherein the signals include a plurality of optical signals;
• processing the plurality of command signals and plurality of address signals;
• and
• simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals.

A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

• providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated;
• receiving a plurality of command signals and a plurality of address signals via the bus, wherein the signals include a plurality of RF signals;
• processing the plurality of command signals and plurality of address signals;
• and
• simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals.