Convey Computer
Richardson, TX, US· latest recorded location
Convey Computer is named on 9 US grants and 12 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 9
- Published applications
- 12
- Inventors
- 11
- Granted in 2026 so far
- 0
- Most recent grant
- 21 Apr 2015
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2009 | 0 | 4 |
| 2010 | 0 | 4 |
| 2011 | 0 | 0 |
| 2012 | 4 | 1 |
| 2013 | 3 | 1 |
| 2014 | 0 | 0 |
| 2015 | 2 | 2 |
By publication year.
Technology areas
Share of 21 documents
Recent patents
- Multiple data channel memory module architecture21 Apr 2015US 9,015,399 B2
- Multistage development workflow for generating a custom instruction set reconfigurable processor3 Mar 2015US 8,972,958 B1
- Compiler for generating an executable comprising instructions for a plurality of different instruction sets15 Oct 2013US 8,561,037 B2
- Memory interleave for heterogeneous computing14 May 2013US 8,443,147 B2
- Systems and methods for mapping a neighborhood of data to general registers of a processing element16 Apr 2013US 8,423,745 B1
- Multiple data channel memory module architecture23 Jul 2015US 2015/0206561 A1
- Multistate development workflow for generating a custom instruction set reconfigurable processor21 May 2015US 2015/0143350 A1
- Systems and methods for efficient scheduling of concurrent applications in multithreaded processors12 Dec 2013US 2013/0332711 A1
- Memory interleave for heterogeneous computing29 Mar 2012US 2012/0079177 A1
- Dynamically-selectable vector register partitioning6 May 2010US 2010/0115233 A1
Most cited
By later US patents
- Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor105US 8,205,066 B22012
- Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set95US 8,156,307 B22012
- Dispatch mechanism for dispatching instructions from a host processor to a co-processor90US 8,122,229 B22012
- Compiler for generating an executable comprising instructions for a plurality of different instruction sets87US 8,561,037 B22013
- Systems and methods for mapping a neighborhood of data to general registers of a processing element75US 8,423,745 B12013