Multiple data channel memory module architecture

A memory module comprising:

• memory enabling simultaneous access to a plurality of sub cache blocks for servicing a cache block access;
• a plurality of independent data channels for accessing said memory, each data channel supporting a sub cache block access, wherein an access bus of said memory module is partitioned into eight independent eight-byte sub-buses such that multiple ones of said plurality of independent data channels may be used for servicing said cache-block access;
• an external address/control channel for receiving address and control information for memory operations for at least one of the pluralities in the cache block to be serviced by the plurality of independent data channels, wherein said external address/control channel is separate from the plurality of independent data channels;
• a plurality of internal address/control channels for carrying address and control information for the plurality of independent data channels, such that an address and a request type is independently supported for each of said eight-byte sub-buses individually;
• and
• control logic operable to receive, via the external address/control channel, encoded address and control information, and decode the received address and control information to result in address and control information for the plurality of internal address/control channels.

A memory module comprising:

• memory enabling simultaneous access to a plurality of sub cache blocks for servicing a cache block access;
• a plurality of independent data channels communicatively coupled to said memory, wherein each of the plurality of independent data channels is operable to carry a sub-cache-block of data of at least one of the pluralities of sub-cache blocks in the cache block for independent memory access operations, wherein an access bus of said memory module is partitioned into eight independent eight-byte sub-buses such that multiple ones of said plurality of independent data channels may be used for servicing said cache-block access;
• and
• a separate address/control channel dedicated for only receiving address and control information for memory operations to be serviced by the plurality of independent data channels such that an address and a request type is independently supported for each of said eight-byte sub-buses individually.

A method of servicing memory access requests, the method comprising:

• receiving, at a memory of a memory module enabling simultaneous access to a plurality of sub cache blocks for servicing a cache block access, via an external address/control channel, encoded address and control information for a plurality of independent memory access operations for at least one of the pluralities of sub cache blocks, wherein an access bus of said memory module is partitioned into eight independent eight-byte sub-buses such that multiple ones of said eight independent eight-byte sub-buses may be used for servicing said cache-block access, said external address/control channel being configured such that an address and a request type is independently supported for each of said eight-byte sub-buses individually;
• decoding, by control logic of the memory module, the received encoded address and control information into information for a plurality of internal independent address/control channels within the memory module;
• and
• carrying data for servicing the plurality of independent memory access operations as defined by the information on the plurality of internal independent address/control channels via a plurality of independent data channels of the memory module, wherein the external address/control channel is separate from the plurality of independent data channels.