US 8,972,958 B1Granted

Multistage development workflow for generating a custom instruction set reconfigurable processor

AssigneeConvey Computer

InventorTony Brewer

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Abstract

Systems and systems which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions. A framework generator and hardware description language complier are also included in the multistage workflow of embodiments.

Claims30

Dependent claims

A method comprising:

parsing, by a compiler, statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor;
analyzing, by the compiler, the statements of input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding:
access capabilities of the custom instructions;
calling capabilities of the custom instructions;
and
support capabilities of the custom instructions;
generating, by the compiler, a custom instruction description file including the custom instructions;
generating, by the compiler, a framework capabilities description file including information regarding the capabilities of the reconfigurable processor that are being utilized by the custom instructions;
adapting, by a timing manager, the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file;
and
adapting, by the timing manager, the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file.

8 more elements

An apparatus comprising:

one or more computer processors implementing:
a compiler adapted to:
parse statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor;
generate a custom instruction description file including the custom instructions;
analyze the statements of the input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding:
access capabilities of the custom instructions;
calling capabilities of the custom instructions;
and
support capabilities of the custom instructions;
generate a framework capabilities description file including information regarding capabilities of the reconfigurable processor that are being utilized by the custom instructions;
a timing manager configured to:
adapt the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file;
and
adapt the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file;
and
at least one memory coupled to the one or more computer processors.

13 more elements

Dependencies are inferred from the claim text.