Memory interleave for heterogeneous computing

A system comprising:

• a memory;
• a plurality of memory controllers for said memory;
• a first compute element that issues physical addresses for cache-block oriented access requests to said memory;
• a second compute element that issues virtual addresses for sub-cache-block oriented access requests to said memory, wherein said first and second compute elements share a common physical and virtual address space of the memory;
• a memory interleave system that receives the physical address for the cache-block oriented access requests issued by the first compute element and receives the virtual addresses for the sub-cache-block oriented access requests issued by the second compute element, and said memory interleave system determines, for each of the received cache-block oriented and sub-cache-block oriented access requests, one of the plurality of memory controllers to direct the access request for interleaving the cache-block oriented and sub-cache-block oriented access requests.

A system comprising:

• non-sequential access memory;
• a cache-access path in which cache-block data is communicated between said non-sequential access memory and a cache memory;
• and
• a direct-access path in which sub-cache-block data is communicated to/from said non-sequential access memory;
• and
• a memory interleave system for interleaving accesses to said non-sequential access memory via the cache-access path and the direct-access path to minimize hot spots within said non-sequential access memory;
• wherein said memory interleave system receives a physical address for a cache-block memory access request via the cache-access path, and wherein said memory interleave system receives a virtual address for a sub-cache-block memory access request via the direct-access path;
• and
• wherein the memory interleave system determines said interleaving using the received physical address for the cache-block memory access request and the received virtual address for the sub-cache-block memory access request without requiring the virtual address to first be translated into a physical address.

A method for performing memory interleaving, said method comprising:

• receiving, by a memory interleave system, a cache-block oriented memory access request from a host processor of a system, said host processor having a fixed instruction set that defines instructions that the host processor can execute;
• receiving, by the memory interleave system, a sub-cache-block oriented memory access request from a co-processor of the system, said co-processor comprising reconfigurable logic that is reconfigurable to have any one of a plurality of predefined extended instruction sets for extending the fixed instruction set of the host processor for processing instructions of an executable file, each of said plurality of predefined extended instruction sets defining a plurality of instructions that the co-processor can execute, wherein said plurality of instructions comprise extended instructions that are not natively defined by the fixed instruction set of the host processor;
• and
• performing memory interleaving, by the memory interleave system, for the received cache-block oriented and sub-cache-block oriented memory access requests.