Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor

A system for processing data comprising:

• at least one manufactured host processor having a predefined instruction set that is fixed such that it is not modifiable by a consumer;
• a co-processor comprising:
• at least one application engine having at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different application-specific personalities, wherein each of the plurality of different application-specific personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor's instruction set, thereby extending the instruction set of the host processor, and
• a virtual memory and instruction decode infrastructure common to all the plurality of different application-specific personalities;
• and
• wherein said manufactured host processor and said co-processor are operable to execute an executable file that contains both native instructions that are natively supported by the host processor's instruction set and extended instructions that are not natively supported by the host processor's instruction set, wherein said extended instructions are present in the executable file as data to be written to a memory by one or more of said native instructions, whereby said native instructions of the executable file are processed by the host processor and said host processor unknowingly dispatches extended instructions of the executable file to the co-processor for processing as a result of said host processor executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

A co-processor comprising:

• a system interface infrastructure for interfacing with a manufactured host processor that has a predefined instruction set that is fixed such that the predefined instruction set is not modifiable by a consumer,
• at least one application engine having at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different, mutually-exclusive application-specific vector processing personalities, wherein each of the plurality of application-specific vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor's instruction set, thereby extending the fixed instruction set of the host processor;
• a co-processor infrastructure common to all the plurality of different application-specific vector processing personalities;
• and
• wherein said co-processor is operable with said manufactured host processor to execute an executable file that contains both native instructions that are natively supported by the host processor's instruction set and extended instructions that are not natively supported by the host processor's instruction set, wherein said extended instructions are present in the executable file as data to be written to a memory by one or more of said native instructions, whereby said native instructions of the executable file are processed by the host processor and said extended instructions of the executable file are processed by the co-processor.

A system comprising:

• a host processor having a predefined fixed instruction set;
• and
• a co-processor, said co-processor including
• at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different, mutually-exclusive vector processing personalities, wherein each of the plurality of different vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor's instruction set, thereby extending the predefined fixed instruction set of the host processor, and
• a virtual memory and instruction decode infrastructure that is common to all the plurality of different vector processing personalities;
• wherein an executable file executing on said host processor contains both native instructions that are natively supported by the host processor's instruction set and extended instructions that are not natively supported by the host processor's instruction set, and wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory that is accessible by said co-processor.

A system comprising:

• a manufactured host processor having a predefined fixed instruction set that is not modifiable by a consumer;
• a dynamically reconfigurable co-processor comprising reconfigurable function units that can be dynamically configured, at system run-time, to fully possess any selected one of a plurality of different, mutually-exclusive vector processing personalities for performing corresponding operations of the selected vector processing personality, wherein each of the plurality of different vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor's instruction set, thereby extending the fixed instruction set of the host processor;
• said dynamically reconfigurable co-processor further comprising an infrastructure that is common to all the plurality of different vector processing personalities;
• wherein said dynamically reconfigurable co-processor is operable with said manufactured host processor to execute an executable file that contains both native instructions that are natively supported by the host processor's instruction set and extended instructions that are not natively supported by the host processor's instruction set, wherein said extended instructions are present in the executable file as data to be loaded to a memory by one or more of said native instructions;
• and
• wherein the executable file contains native instructions that when executed by the host processor causes the host processor to unknowingly dispatch said extended instructions to said co-processor by loading the extended instructions to a pre-designated portion of said memory that is accessible by said co-processor.

A method comprising:

• initiating an executable file on a manufactured host processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, wherein the executable file contains native instructions that are natively supported by the host processor's predefined instruction set and extended instructions that are not natively supported by the host processor's predefined instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a designated portion of a memory that is accessible by a reconfigurable co-processor;
• configuring said reconfigurable co-processor to fully possess a selected one of a plurality of different, mutually-exclusive vector processing personalities for processing a portion of the instructions of the executable file, wherein each of the plurality of different predefined vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor's instruction set, thereby extending the fixed instruction set of the host processor;
• processing the instructions of the executable file, wherein said native instructions of the executable file are processed by the host processor and said extended instructions of the executable file are processed by the reconfigurable co-processor.

A method comprising:

• initiating an executable file on a manufactured host processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, wherein the executable file contains native instructions that are natively supported by the host processor's predefined instruction set and extended instructions that are not natively supported by the host processor's predefined instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory;
• determining one of a plurality of different, mutually-exclusive vector processing personalities to load to a dynamically reconfigurable co-processor for processing a portion of the instructions of the executable file, wherein the determined vector processing personality defines an extended instruction set that comprises instructions for performing vector oriented operations that are not natively supported by the host processor's predefined instruction set, thereby extending the host processor's instruction set;
• when determined that the determined vector processing personality is not present on the dynamically reconfigurable co-processor, fully loading, at system run-time, the determined vector processing personality to the dynamically reconfigurable co-processor;
• and
• processing the instructions of the executable file, wherein the native instructions of the executable file are processed by the host processor and the extended instructions of the executable file are processed by the dynamically reconfigurable co-processor, wherein said host processor unknowingly dispatches said extended instructions of the executable file to the co-processor as a result of executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

A system comprising:

• a manufactured host processor implemented on a first integrated circuit and comprising a predefined fixed instruction set that is not modifiable by a consumer;
• and
• a co-processor implemented external to said first integrated circuit and comprising reconfigurable logic for dynamically reconfiguring the co-processor to possess any of a plurality of different vector processing personalities, wherein each of said plurality of different vector processing personalities comprises an extended instruction set providing extended instructions not natively supported by the host processor's instruction set, thereby extending the host processor's instruction set;
• and
• wherein said manufactured host processor and said co-processor are operable to execute an executable file that contains both native instructions that are natively supported by the host processor's instruction set and extended instructions that are not natively supported by the host processor's instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory, whereby said host processor unknowingly dispatches said extended instructions of the executable file to the co-processor as a result of executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.