Dispatch mechanism for dispatching instructions from a host processor to a co-processor

A method comprising:

• executing, by a host processor, a first portion of instructions of an executable file;
• dispatching instructions of the executable file from the host processor to an external heterogeneous co-processor that is external to an integrated circuit on which said host processor is implemented, wherein said host processor has a first instruction set and wherein said heterogeneous co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor's instruction set to be any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the first instruction set, wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set;
• wherein said dispatching comprises writing, by said host processor, an address of the at least one extended instruction included in said executable file to a designated portion of memory;
• detecting, by said co-processor, said address of said the at least one extended instruction in the designated portion of memory;
• writing information to said designated portion of memory to specify one of the plurality of predefined extended instruction sets to be employed on the co-processor for processing the at least one extended instruction;
• and
• executing, by said co-processor, said at least one extended instruction.

A method comprising:

• issuing extended instructions of an executable file for processing by a co-processor, wherein a host processor and said co-processor each process a portion of instructions of said executable file, and wherein the host processor is a manufactured processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, and wherein the co-processor is reconfigurable to have any of a plurality of predefined extended instruction sets for extending the fixed instruction set of the host processor, wherein each of the extended instruction sets provides extended instructions that are not natively supported by the host processor's instruction set, wherein at least one of the extended instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the host processor's instruction set, and wherein the host processor's instruction set does not include a native instruction for dispatching said extended instructions to said co-processor;
• monitoring, by the co-processor, an issue memory structure;
• said issuing comprises writing, by the host processor, to a command memory structure an address of at least one extended instruction included in the executable file to be processed by the co-processor;
• writing, by the host processor, a predefined value to the issue memory structure for triggering processing of the at least one extended instruction;
• and
• responsive to detecting said predefined value in the issue memory structure, said co-processor processing the at least one extended instruction included in the executable file, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

A method for issuing instructions of an executable file for processing by a co-processor, the method comprising:

• executing said executable file on a manufactured host processor that is implemented on a first integrated circuit and that has a fixed instruction set that is not modifiable by a consumer;
• monitoring, by the co-processor, an issue memory structure that is in a common global physical address space that is shared by said host processor and said co-processor, wherein the co-processor is implemented external to said first integrated circuit and has an extended instruction set that extends the instruction set of the host processor such that the extended instruction set provides extended instructions not natively supported by the host processor's instruction set, and wherein the executable file includes at least one of said extended instructions and at least one instruction that is native to the host processor's instruction set;
• writing, by the host processor, to a command memory structure an address of the at least one extended instruction included in the executable file to be processed by the co-processor, wherein said command memory structure is in said common global physical address space that is shared by said host processor and said co-processor;
• writing, by the host processor, a predefined value to the issue memory structure for triggering processing of the at least one extended instruction included in the executable file;
• and
• responsive to detecting said predefined value in the issue memory structure, said co-processor processing the at least one extended instruction included in the executable file;
• wherein said monitoring said issue memory structure comprises:
• monitoring, by said co-processor, cache line activity of the issue memory structure, and
• responsive to detecting cache line activity occurring in the issue memory structure, said co-processor determining whether the issue memory structure contains said predefined value for triggering processing of the at least one extended instruction addressed at the address in the command memory structure.

A method comprising:

• processing instructions of an executable file by a system that comprises a manufactured host processor that is implemented on a first integrated circuit and having a predefined fixed instruction set that is not modifiable by a consumer, and a heterogeneous co-processor that is implemented external to said first integrated circuit and having an extended instruction set that extends said fixed instruction set of the host processor such that the extended instruction set provides extended instructions not natively supported by the host processor's fixed instruction set, wherein the executable file comprises at least one segment of instructions that are native to the host processor's fixed instruction set and at least one segment of said extended instructions;
• maintaining cache coherency between the at least one host processor and the at least one heterogeneous co-processor;
• writing to a command memory structure, by the host processor, a virtual address of a first instruction of the at least one segment of said extended instructions, wherein said host processor and said heterogeneous co-processor share a common global virtual address space;
• and
• triggering the co-processor to begin execution of said at least one segment of said extended instructions at the virtual address by said host processor writing a value to an issue memory structure.

A system comprising:

• a plurality of processors comprising at least a manufactured host processor implemented on a first integrated circuit and a heterogeneous co-processor implemented external to said first integrated circuit, wherein the host processor has a predefined fixed instruction set that is not modifiable by a consumer and wherein the heterogeneous co-processor is reconfigurable to have any of a plurality of predefined extended instruction sets for extending the host processor's instruction set such that each extended instruction set provides extended instructions not natively supported by the host processor's instruction set, wherein the host processor's instruction set does not include a native instruction for dispatching said extended instructions to said co-processor, and wherein the host processor processes instructions included in an executable file that are native to the host processor's instruction set and said heterogeneous co-processor processes at least one of said extended instructions included in the executable file;
• a communication bus for communicatively interconnecting said host processor on said first integrated circuit with said external heterogeneous co-processor;
• a command memory structure to which said host processor identifies said at least one of said extended instructions of the executable file that are to be processed by the co-processor;
• and
• an issue memory structure that indicates which of said host processor and heterogeneous co-processor possesses ownership of said command memory structure, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

A system comprising:

• at least one manufactured host processor that is implemented on a first integrated circuit and having a fixed instruction set that is not modifiable by a consumer and comprising a first main memory;
• at least one heterogeneous co-processor that is implemented external to said first integrated circuit and having a second instruction set that extends said host processor's instruction set such that the extended instruction set provides extended instructions not natively supported by the host processor's fixed instruction set and said at least one heterogeneous co-processor comprising a second main memory, wherein said first main memory and said second main memory are in a common global physical memory space, and wherein said host processor's fixed instruction set does not include a native instruction for dispatching said extended instructions to said at least one heterogeneous co-processor;
• said at least one host processor and said at least one heterogeneous co-processor each comprising a respective local cache, wherein cache coherency is maintained between the at least one host processor and at least one heterogeneous co-processor;
• and
• a designated portion of at least one of said first main memory and said second main memory, wherein when the at least one host processor is executing an executable file that includes instructions natively supported by the host processor's fixed instruction set and at least one of said extended instructions, said at least one host processor uses at least one instruction of its fixed instruction set to store to said designated portion identification of said at least one of said extended instructions included in said executable file for processing by said at least one heterogeneous co-processor.

A method for executing instructions of an executable file by a manufactured host processor implemented on a first integrated circuit and a co-processor that is implemented external to said first integrated circuit, wherein said manufactured host processor has a fixed instruction set that is not modifiable by a consumer and the co-processor has an extended instruction set that includes extended instructions not natively supported by the fixed instruction set of the host processor, wherein said executable file includes at least one instruction of said host processor's fixed instruction set and at least one of said extended instructions, and wherein the host processor's fixed instruction set does not include a native instruction for issuing said at least one of said extended instructions to said at least one heterogeneous co-processor, the method comprising:

• monitoring, by the co-processor, an issue memory structure, wherein said monitoring said issue memory structure comprises:
• monitoring, by said co-processor, cache line activity of an issue memory structure, and
• responsive to detecting cache line activity occurring in the issue memory structure, said co-processor determining whether the issue memory structure contains a predefined value for triggering processing of said at least one of said extended instructions of the executable file that is addressed at an address contained in a command memory structure;
• and
• responsive to detecting by the co-processor said predefined value in the issue memory structure, said co-processor processing the at least one of said extended instructions of the executable file that is addressed at the address contained in the command memory structure, wherein said issue memory structure and said command memory structure are in a common global physical address space that is shared by said host processor and said co-processor.

A method comprising:

• executing, by a manufactured host processor that is implemented on a first die, a first portion of instructions of an executable file, wherein said manufactured host processor has a first instruction set that is fixed such that it is not modifiable by a consumer;
• dispatching instructions of the executable file from the host processor to a co-processor that is not implemented on said first die, wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor's instruction set to be any of a plurality of predefined extended instruction sets for extending the first instruction set of the host processor, wherein each of the extended instruction sets provides instructions not natively supported by the first instruction set, wherein at least one of the instructions of at least one of the extended instruction sets is included in the executable file in addition to instructions that are native to the first instruction set, and wherein said first instruction set does not natively support dispatching of the at least one extended instruction to said heterogeneous co-processor;
• said dispatching comprising writing, by said host processor, an address of the at least one extended instruction of said executable file to a designated portion of a shared memory;
• detecting, by said co-processor, said address of the at least one extended instruction in the designated portion of memory;
• and
• executing, by said co-processor, said at least one extended instruction.