Dynamically-selectable vector register partitioning
AssigneeConvey Computer
InventorsTony Brewer, Steven J. Wallach
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AssigneeConvey Computer
InventorsTony Brewer, Steven J. Wallach
Estimating the term…
The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention.
A method for processing data comprising:
A co-processor in a multi-processor system, the co-processor comprising:
A system for processing data comprising:
A multi-processor system comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.