Ascenium, Inc.
Mountain View, CA, US· latest recorded location
Ascenium, Inc. is named on 8 US grants and 35 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 8
- Published applications
- 35
- Inventors
- 11
- Granted in 2026 so far
- 5
- Most recent grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2006 | 0 | 1 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 1 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 1 |
| 2021 | 0 | 0 |
| 2022 | 0 | 8 |
| 2023 | 0 | 9 |
| 2024 | 0 | 8 |
| 2025 | 2 | 6 |
| 2026 | 5 | 1 |
By publication year. 2026 runs to 8 Oct.
Technology areas
Share of 43 documents
Recent patents
- Parallel processing architecture for branch path suppression29 Sep 2026US 12,748,638 B2
- Parallel processing architecture with block move support22 Sep 2026US 12,743,377 B2
- Load latency amelioration using bunch buffers8 Sep 2026US 12,730,668 B2
- Highly parallel processing architecture with out-of-order resolution11 Aug 2026US 12,705,092 B2
- Parallel processing architecture with distributed register files17 Mar 2026US 12,578,991 B2
- Generating iteration transfer information for code execution with a compute slice microarchitecture21 May 2026US 2026/0140778 A1
- Memory dependence prediction in a parallel architecture with compute slices18 Dec 2025US 2025/0383878 A1
- Global memory disambiguation for a parallel architecture with compute slices6 Nov 2025US 2025/0341970 A1
- Local memory disambiguation for a parallel architecture with compute slices2 Oct 2025US 2025/0306930 A1
- Compiler generated hyperblocks in a parallel architecture with compute slices21 Aug 2025US 2025/0265088 A1
Most cited
By later US patents