Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime

A computational system comprising:

• a successively configurable data pipe (hereafter as data pipe), a successively configurable instruction pipe (hereafter as instruction pipe), a reconfigurable computational array (hereafter as array), and a memory;
• the data pipe communicatively coupled with the array and the memory, and successively configured for communicating input operating data from the memory and to the array, wherein the data pipe executes a plurality of data directives that control data movement to and from the memory, to and from the array, and to the instruction pipe;
• the instruction pipe communicatively coupled with the array and the memory, and successively configured for communicating reconfiguration data from the memory to the array;
• and
• the array comprising a plurality of iterators successively reconfigured in parallel by the instruction pipe for asserting input operating data into the array from the data pipe and latching data processing results comprising output operating data from the array for the data pipe and preserving output operating data from one data processing cycle to use as input operating data in the next data processing cycle, wherein each iterator is clocked by a same data processing cycle pulse, a plurality of muxes successively reconfigured in parallel by the instruction pipe for performing 3 to 1 bitwise data processing, and a plurality of cones successively reconfigured in parallel by the instruction pipe for performing logic on a plurality of bits, and the array organized for a plurality of successive reconfigurations at runtime, wherein each cone comprises a circuit providing logic operations useful for computation that require more than three inputs to synthesize one output, including but not limited to static or dynamic bit and word shifters, adders or their components, wide logic, multipliers or their components, configurable bit to word circuitry, and zero counters.

A runtime dynamically configurable processor for general purpose processing of software applications, comprising:

• a reconfigurable computational array (hereafter as array) comprising a plurality of logic elements;
• the logic elements reconfigured to perform logic operations and to select inputs from other directly connected logic elements interconnected in a dedicated unidirectional toroidal static fashion;
• a memory for storing operating data, reconfiguration data and data directives;
• a successively configurable data pipe (hereafter as data pipe) that fetches data directives and communicates operating data directionally between the memory and the array in accordance with the data pipe executing the data directives;
• and
• a successively configurable instruction pipe (hereafter as instruction pipe) that fetches and communicates reconfiguration data to the array from the memory to reconfigure the logic elements;
• wherein the data directives control all data movement to and from the memory, to and from the array, and to the instruction pipe.