Load latency amelioration using bunch buffers

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, wherein the control words that are provided enable parallel execution of tasks, wherein the tasks include two or more tasks that are independent of one another;
• loading sets of control word bits into buffers, wherein each buffer is associated with and coupled to a unique compute element within the array of compute elements, and wherein the sets of control word bits provide operational control for the compute element with which it is associated;
• and
• executing operations within the array of compute elements, wherein the operations are based on a selected set of control word bits, wherein the selected set of control word bits comprise a control word bunch.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, wherein the control words that are provided enable parallel execution of tasks, wherein the tasks include two or more tasks that are independent of one another;
• load sets of control word bits into buffers, wherein each buffer is associated with and coupled to a unique compute element within the array of compute elements, and wherein the sets of control word bits provide operational control for the compute element with which it is associated;
• and
• execute operations within the array of compute elements, wherein the operations are based on a selected set of control word bits, wherein the selected set of control word bits comprise a control word bunch.