Parallel processing architecture with block move support

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, wherein the array of compute elements is coupled to at least one data cache, wherein the data cache provides memory storage for the array of compute elements;
• providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler;
• generating a load address and a store address, wherein the load address and the store address comprise memory block move addresses, and wherein the memory block move addresses point to memory storage locations in the at least one data cache;
• coupling load buffers located adjacent to at least one edge of the array of compute elements, wherein the load buffers provide storage for data obtained from the load address and a dataless store address;
• and
• executing a memory block move, based on the memory block move addresses, wherein data for the memory block move is transferred outside of the array of compute elements.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, wherein the array of compute elements is coupled to at least one data cache, wherein the data cache provides memory storage for the array of compute elements;
• provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler;
• generate a load address and a store address, wherein the load address and the store address comprise memory block move addresses, and wherein the memory block move addresses point to memory storage locations in the at least one data cache;
• couple load buffers located adjacent to at least one edge of the array of compute elements, wherein the load buffers provide storage for data obtained from the load address and a dataless store address;
• and
• execute a memory block move, based on the memory block move addresses, wherein data for the memory block move is transferred outside of the array of compute elements.