Parallel processing architecture for branch path suppression

A computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, and wherein the control includes a branch;
• mapping a plurality of compute elements within the array of compute elements, wherein the mapping distributes parallelized operations to the plurality of compute elements, wherein the mapping is determined by the compiler, and wherein a column of compute elements within the plurality of compute elements is enabled to perform vertical data access suppression and a row of compute elements is enabled to perform horizontal data access suppression;
• executing both sides of the branch in the array of compute elements, wherein the executing includes making a branch decision;
• and
• suppressing data accesses produced by a branch operation, based on the branch decision and an invalid indication, wherein the invalid indication is propagated among two or more of the compute elements.

A computer system for parallel processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, and wherein the control includes a branch;
• map a plurality of compute elements within the array of compute elements, wherein the mapping distributes parallelized operations to the plurality of compute elements, wherein the mapping is determined by the compiler, and wherein a column of compute elements within the plurality of compute elements is enabled to perform vertical data access suppression and a row of compute elements is enabled to perform horizontal data access suppression;
• execute both sides of the branch in the array of compute elements, wherein the executing includes making a branch decision;
• and
• suppress data accesses produced by a branch operation, based on the branch decision and an invalid indication, wherein the invalid indication is propagated among two or more of the compute elements.