Parallel processing architecture with distributed register files

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• controlling the array of compute elements on a cycle-by-cycle basis, wherein the controlling is enabled by a stream of wide, variable length, control words generated by the compiler;
• mapping virtual registers to a plurality of physical register files distributed among one or more of the compute elements, wherein the mapping is performed by the compiler, and wherein the mapping of the virtual registers includes renaming by the compiler;
• and
• executing operations contained in the control words, wherein the renaming by the compiler enables distributed execution of operations, and wherein the operations are enabled by at least one of the plurality of distributed physical register files, and wherein the distributed execution of operations occurs in two or more compute elements within the array of compute elements.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• control the array of compute elements on a cycle-by-cycle basis, wherein the controlling is enabled by a stream of wide, variable length, control words generated by the compiler;
• map virtual registers to a plurality of physical register files distributed among one or more of the compute elements, wherein the mapping is performed by the compiler, and wherein mapping of the virtual registers includes renaming by the compiler;
• and
• execute operations contained in the control words, wherein the renaming by the compiler enables distributed execution of operations, and wherein the operations are enabled by at least one of the plurality of distributed physical register files, and wherein the distributed execution of operations occurs in two or more compute elements within the array of compute elements.