Highly parallel processing architecture with out-of-order resolution

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, and wherein the array of compute elements is coupled to supporting logic and to memory, which together with the array of compute elements comprises compute hardware;
• providing a set of directions to the hardware, through a control word generated by the compiler, for compute element operation;
• augmenting the set of directions with data access ordering information, wherein data access ordering is performed by the compute hardware, wherein the ordering information includes ordering information for a single architectural cycle, wherein the single architectural cycle contains multiple compute element operations;
• and
• executing a compiled task on the array of compute elements, based on the set of directions that was augmented.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements, and wherein the array of compute elements is coupled to supporting logic and to memory, which together with the array of compute elements comprises compute hardware;
• provide a set of directions to the hardware, through a control word generated by the compiler, for compute element operation;
• augment the set of directions with data access ordering information, wherein data access ordering is performed by the compute hardware, wherein the ordering information includes ordering information for a single architectural cycle, wherein the single architectural cycle contains multiple compute element operations;
• and
• execute a compiled task on the array of compute elements, based on the set of directions that was augmented.