Generating iteration transfer information for code execution with a compute slice microarchitecture

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a processor core, wherein the processor core is configured to execute instructions associated with an instruction set architecture (ISA), wherein the processor core comprises a plurality of compute slices, a plurality of barrier register files, and a control unit, wherein each compute slice within the plurality of compute slices includes at least one arithmetic logic unit (ALU), a local register file, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register file in the plurality of barrier register files;
• evaluating code associated with the ISA, wherein the code includes a first loop, wherein the evaluating includes generating iteration transfer information associated with the first loop;
• distributing each slice task within a plurality of slice tasks associated with the first loop to a compute slice within the plurality of compute slices;
• and
• executing, by the processor core, the plurality of slice tasks, wherein data forwarding between successive compute slices within the plurality of compute slices is based on the plurality of barrier register files and the iteration transfer information.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core is configured to execute instructions associated with an instruction set architecture (ISA), wherein the processor core comprises a plurality of compute slices, a plurality of barrier register files, and a control unit, wherein each compute slice within the plurality of compute slices includes at least one arithmetic logic unit (ALU), a local register file, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register file in the plurality of barrier register files;
• evaluate code associated with the ISA, wherein the code includes a first loop, wherein evaluating includes generating iteration transfer information associated with the first loop;
• distribute each slice task within a plurality of slice tasks associated with the first loop to a compute slice within the plurality of compute slices;
• and
• execute, by the processor core, the plurality of slice tasks, wherein data forwarding between successive compute slices within the plurality of compute slices is based on the plurality of barrier register files and the iteration transfer information.