Y10S 148/133
Reflow oxides and glasses
Y10S148/133 (Reflow oxides and glasses) appears on 73 US grants and 0 published applications in this corpus.
Search patents in Y10S- Granted patents
- 73
- Published applications
- 0
- Assignees
- 41
- Inventors
- 129
- Latest grant
- 16 Nov 1999
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 4 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 0 | 0 |
| 1988 | 4 | 0 |
| 1989 | 3 | 0 |
| 1990 | 4 | 0 |
| 1991 | 9 | 0 |
| 1992 | 8 | 0 |
| 1993 | 5 | 0 |
| 1994 | 7 | 0 |
| 1995 | 9 | 0 |
| 1996 | 4 | 0 |
| 1997 | 2 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Method of forming a via hole filled with a conducting material, and separater from a gate structure by an insulating material16 Nov 1999US 5,985,745 ASony Corporation
- Method and apparatus for reflowing and annealing borophosphosilicate glass27 Oct 1998US 5,828,036 AUnited Microelectronics Corp.
- Method for optimizing thermal budgets in fabricating semiconductors8 Jul 1997US 5,646,075 AMicron Technology, Inc.
- Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches24 Jun 1997US 5,641,704 AFrance Telecom
- Method of producing semiconductor device with viscous flow of silicon oxide17 Dec 1996US 5,584,964 AMatsushita Electric Industrial Co., Ltd.
No published applications in this class yet.
Most cited
By later US patents
- Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing438US 4,962,063 AAPPLIED Materials.Inc. · 1990
- Method for forming trench isolation structures190US 4,571,819 ANCR Corporation · 1986
- High temperature interconnect system for an integrated circuit147US 4,920,071 AFairchild Camera and Instrument Corporation · 1990
- Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines92US 4,192,059 ARockwell International Corporation · 1980
- Method for planarization of a semiconductor device prior to metallization83US 4,795,722 ATexas Instruments Incorporated · 1989