H04L 7/0045
Correction by a latch cascade
Official title: {Correction by a latch cascade}
H04L7/0045 (Correction by a latch cascade) appears on 155 US grants and 115 published applications in this corpus.
Search patents in H04L- Granted patents
- 155
- Published applications
- 115
- Assignees
- 98
- Inventors
- 311
- Latest grant
- 17 Mar 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 2 | 0 |
| 1996 | 6 | 0 |
| 1997 | 4 | 0 |
| 1998 | 3 | 0 |
| 1999 | 5 | 0 |
| 2000 | 0 | 0 |
| 2001 | 3 | 0 |
| 2002 | 3 | 7 |
| 2003 | 5 | 11 |
| 2004 | 3 | 6 |
| 2005 | 3 | 5 |
| 2006 | 12 | 4 |
| 2007 | 8 | 2 |
| 2008 | 2 | 5 |
| 2009 | 2 | 2 |
| 2010 | 3 | 5 |
| 2011 | 3 | 6 |
| 2012 | 3 | 2 |
| 2013 | 5 | 2 |
| 2014 | 3 | 5 |
| 2015 | 13 | 8 |
| 2016 | 10 | 10 |
| 2017 | 8 | 5 |
| 2018 | 9 | 7 |
| 2019 | 4 | 7 |
| 2020 | 4 | 3 |
| 2021 | 6 | 4 |
| 2022 | 4 | 4 |
| 2023 | 2 | 0 |
| 2024 | 2 | 5 |
| 2025 | 3 | 0 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Methods and apparatus to reduce retimer latency and jitter17 Mar 2026US 12,580,720 B2Texas Instruments Incorporated
- Phase-based lock detector with programmable frequency offset tolerance2 Dec 2025US 12,489,598 B2Rambus Inc.
- Low latency data handoff using phase rotation and clock gapping29 Apr 2025US 12,289,391 B2Ciena Corporation
- Clock synchronization system, signal synchronization control method, and storage medium28 Jan 2025US 12,210,934 B2Tencent Technology (Shenzhen) Company Limited
- Clock data recovery circuit28 May 2024US 11,994,901 B2Texas Instruments Incorporated
- Clock data recovery circuit15 Aug 2024US 2024/0272670 A1Texas Instruments Incorporated
- Methods and apparatus to reduce retimer latency and jitter1 Aug 2024US 2024/0259175 A1Texas Instruments Incorporated
- Phase-Based Lock Detector with Programmable Frequency Offset Tolerance23 May 2024US 2024/0171368 A1Rambus Inc.
- Methods and apparatus to reduce retimer latency and jitter4 Apr 2024US 2024/0113851 A1Texas Instruments Incorporated
- Low latency data handoff using phase rotation and clock gapping7 Mar 2024US 2024/0080178 A1Ciena Corporation
Most cited
By later US patents
- Method and apparatus for fail-safe resynchronization with minimum latency94US 6,473,439 B1Rambus Inc. · 2002
- Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock80US 6,535,946 B1National Semiconductor Corporation · 2003
- Synchronizer, method and system for transferring data61US 5,905,766 AFORE Systems, Inc. · 1999
- Synchronizer apparatus for system having at least two clock domains54US 5,256,912 ASun Microsystems, Inc. · 1993
- System for high-speed synchronization across clock domains53US 5,487,092 AInternational Business Machines Corporation · 1996