Synchronizer, method and system for transferring data

A system comprising:

• a first clock domain having a first clock signal at a first clock rate;
• a second clock domain having a second clock signal at a second clock rate, said second clock domain different than said first clock domain;
• a network on which data vectors travel, said network disposed and operating in said first clock domain;
• a memory mechanism for storing data vectors, said memory mechanism disposed and operating in said second clock domain;
• and
• a synchronizer for transferring data from the first clock domain having the first clock signal at the first clock rate to the second clock domain having the second clock signal at the second clock rate comprising:
• a mechanism for transferring data from the first clock domain to the second clock domain;
• a mechanism for synchronizing the transfer of data from the first clock domain to the second clock domain by the transferring mechanism, said synchronizing mechanism self-timing based only on the first clock rate and second clock rate without any additional control signals and at any frequency relationship between the first clock rate and second clock rate, said synchronizing mechanism connected with said transferring mechanism, said synchronizer connected with the first clock domain and the second clock domain to receive the first clock signal and the second clock signal wherein during continuous operation of the synchronizing mechanism, the first clock rate, being slower than the second clock rate, changes to a rate faster than the second clock rate or the first rate, being faster than the second clock rate, changes to a rate slower than the second clock rate.

A method for transferring data from a first clock domain having a first clock signal at a first clock rate to a second clock domain having a second clock signal at a second clock rate different from the first clock domain comprising the steps of:

• receiving data at a first clock rate;
• writing the data in holding registers at a first clock rate having leading edges;
• synchronizing the data in the holding registers at the first clock rate with sampling registers at a second clock rate having leading edges based only on the leading edges of the first clock rate and the leading edges of the second clock rate without any additional control signals and at any frequency relationship between the first clock rate and second clock rate;
• transferring the data from the holding registers at the first clock rate to the sampling registers at the second clock rate;
• and
• reading the data in the sampling registers at the second clock rate.

A method for transferring data from a first clock domain having a first clock signal having leading edges at a first clock rate to a second clock domain having a second clock signal having leading edges at a second clock rate different from the first clock domain comprising the steps of:

• receiving data at the first clock rate;
• writing the data in holding registers at a first clock rate;
• synchronizing the data in the holding registers at the first clock rate with sampling registers at a second clock rate so there cannot ever be any overlap between when the data in the holding registers is transferred to the sampling registers and when the data is being written into the holding registers, said synchronizing step based only on the having leading edges of the first clock rate and the having leading edges of the second clock rate without any additional control signals and at any frequency relationship between the first clock rate and the second clock rate:
• transferring the data from the holding registers at the first clock rate to the sampling registers at the second clock rate;
• and
• reading the data in the sampling registers at the second clock rate.

A system comprising:

• a first clock domain having a first clock signal at a first rate;
• a second clock domain having a second clock signal at a second rate, said second clock domain different than said first clock domain;
• a network on which data vectors travel, said network disposed and operating in said first clock domain;
• holding registers in which the data vectors from the data vectors are written, said holding registers disposed and operating to said first clock domain, said holding registers connected with said network;
• sampling registers for storing data vectors, said sampling registers disposed and operating in said second clock domain and connected with the holding registers;
• and
• a synchronizer for transferring data from the first clock domain having the first clock signal at the first clock rate to the second clock domain having the second clock signal at the second clock rate comprising:
• a mechanism for transferring data from the first clock domain to the second clock domain;
• a mechanism for synchronizing the transfer of data from the first clock domain to the second clock domain by the transferring mechanism so there cannot ever be any overlap between when the data in the holding registers is transferred to the sampling registers and when the data is being written into the holding registers, said synchronizing mechanism connected with said transferring mechanism, said synchronizer connected with the first clock domain and the second clock domain to receive the first clock signal and the second clock signal, said synchronizer is self-timing based only on the first clock rate and second clock rate without any additional control signals and at any frequency relationship between the first clock rate and the second clock rate, wherein during continuous operation of the synchronizer, the first clock rate, being slower than the second clock rate, changes to a rate faster than the second clock rate or the first rate, being faster than the second clock rate, changes to a rate slower than the second clock rate.

A synchronizer for transferring data from a first clock domain having a first clock signal at a first clock rate to a second clock domain having a second clock signal at a second clock rate different from the first clock domain comprising:

• a mechanism for transferring data from the first clock domain to the second clock domain, said transferring mechanism transfers N data vectors from the first clock domain to the second clock domain all N data vectors at once, where N is greater than or equal to 1 and is an integer;
• and
• a mechanism for synchronizing the transfer of data from the first clock domain to the second clock domain by the transferring mechanism, said synchronizing mechanism self-timing based only on the first clock rate and second clock rate without any additional control signals, said synchronizing mechanism connected with said transferring mechanism, said transferring mechanism is comprised of holding registers in which the N data vectors are written, said holding registers operating at the first clock rate in the first clock domain, said holding registers connected with the synchronizing mechanism;
• and sampling registers which receive the N data vectors and from which the N data vectors are read at the second clock rate in the second clock domain, said sampling registers connected with the synchronizing mechanism and the holding registers. Wherein the synchronizing mechanism includes a clock sync circuit which is self timing and produces an enable write signal which controls the holding registers and writing of the N data vectors in the holding registers;
• and an said clock sync circuit produces enable read signal which controls the sampling registers and transfer of the N data vectors from the holding registers to the sampling registers and reading of the N data vectors in the sampling registers.