Method and apparatus for fail-safe resynchronization with minimum latency

A synchronous memory bus system comprising:

• a data bus having a first end and a second end;
• a clock source generating a clock signal;
• a clock line carrying the clock signal, the clock line having
• a first clock line segment extending from the first end of the data bus to a turnaround near the second end of the data bus, and
• a second clock line segment extending from the turnaround to the first end of the data bus;
• a first device coupled to the data bus for transmitting data to a second device, including synchronization circuitry that receives a first transmit clock from one of the first and second clock line segments, a receive clock from the other one of the first and second clock line segments, and a second transmit clock in quadrature with the first transmit clock, wherein the receive clock and first transmit clock are mesochronous, the synchronization circuitry comprising:
• a receive clock domain circuit for providing the data clocked by the receive clock;
• a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the second transmit clock;
• a second latching circuit, in parallel with the first latching circuit, for latching the data on a second edge of the second transmit clock;
• a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits;
• and
• a phase measurement circuit, configured to measure a phase difference between the receive clock and first transmit clock and to provide a select signal to the multiplexer in accordance with the phase difference.

A method for synchronizing data between receive and transmit mesochronous clocks, comprising the steps of:

• providing data clocked by a receive clock from a receive clock domain;
• latching the data in a first latching circuit on a first edge of a transmit clock;
• latching the data in a second latching circuit on a second edge of the transmit clock;
• wherein the receive clock and transmit clock are mesochronous and the second latching circuit is coupled to receive the data in parallel with the first latching circuit;
• measuring a phase difference between the receive and transmit clocks and providing a select signal in accordance with the phase difference;
• and
• selecting between the first and second latching circuit based on the select signal.

A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

• a first receive clock domain circuit for providing the data clocked by a first edge of the receive clock;
• a second receive clock domain circuit for providing the data clocked by a second edge of the receive clock;
• two latching circuits, each coupled to an output of a respective of said first and second receive clock domain circuits, for latching the data on an edge of the transmit clock;
• wherein the receive clock and transmit clock are mesochronous and the first receive clock domain circuit and the second receive clock domain circuit are connected in parallel between a source of the data and the two latching circuits;
• a multiplexing circuit, having inputs coupled to outputs of the two latching circuits;
• and
• a phase measurement circuit, configured to measure a phase difference between the receive and transmit clocks and to provide a selection signal to the multiplexer in accordance with the phase differences.

A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

• a receive clock domain circuit for providing the data clocked by the receive clock;
• an intermediate clock domain circuit latching the output of the receive clock domain circuit on an edge of an intermediate clock, wherein the intermediate clock is a phase-interpolated waveform of the receive and transmit clocks and the receive clock and transmit clock are mesochronous;
• and
• a transmit clock domain circuit, coupled to an output of the intermediate clock domain circuit, for latching the data on an edge of the transmit clock.