US 5,256,912 A · Synchronizer apparatus for system having at least two clock domains

Abstract

The present invention, a synchronizer, utlizes a plurality of clocking signals generated by a specialized clocking circuit, in conjunction with synchronizer modules incorporating transparent latches, to synchronize signals passing from a first clock domain to a second clock domain. Two types of synchronizer modules are disclosed, a single synchronizer module and a multiple synchronizer module. Both types of synchronizer modules utilize a "basic synchronizer cell" comprised of two transparent latches in series. The single synchronizer module is comprised of two such basic synchronizer cells, and utilizes a plurality of clocking signals which are coupled to the transparent latches to accomplish synchronization. The multiple synchronizer module, also utilizes a plurality of clocking signals, and is comprised of a plurality of single synchronizer modules coupled in parallel and a synchronizer selector circuit. The multiple synchronizer module operates by initially coupling the signal to be synchronized to the synchronizer selector circuit, which then sequentially couples the signal to successive single synchronizer modules.

Claims9

Dependent claims

A synchronizer for synchronizing signals coupled from a first clock domain operating in accordance with a first clock with a first clock signal having a first frequency, to a second clock domain operating in accordance with a second clock with a second clock signal having second clock pulses at a second frequency, said synchronizer comprising:

clock circuit means for generating a plurality of different clock signals, said plurality of different clock signals including a first master clock signal having at least one first master clock pulse in phase with said second clock signal, and a first slave clock signal having at least one first slave clock pulse 180 degrees out of phase with said second clock signal;
synchronizer circuit means, coupled to said clock circuit means, wherein said synchronizer circuit means utilizes said plurality of different clock signals to synchronize said signals to be synchronized, said synchronizer circuit means having:
a first synchronizer cell circuit comprised of a first plurality of transparent latches;
a second synchronizer cell circuit comprised of a second plurality of transparent latches;
wherein said first synchronizer cell circuit is coupled to said second synchronizer cell circuit.

2 more elements

Dependencies are inferred from the claim text.

Synchronizer apparatus for system having at least two clock domains

Life of this patent

Synchronizer apparatus for system having at least two clock domains

Life of this patent

Abstract

Claims9