System for high-speed synchronization across clock domains

In a digital data system, a clock synchronizer system for transferring digital signals representing a plurality of data words including pad words from an output bus in an external clock domain operating in synchrony with an external clock signal having a frequency and an interval across an asynchronous boundary to an input bus in an internal clock domain operating in synchrony with an internal clock signal having a frequency and an interval, said system comprising:

• input register means coupled to said output bus for receiving said data words in synchrony with said external clock signals;
• prolonged storage register means coupled to said input register means including a plurality N of prolonged storage registers and including means for distributing in synchrony with said external clock signal a plurality N of said data words to said prolonged storage registers to be stored for a plurality N of said external clock intervals;
• sampling register means coupled to said prolonged storage register means including a plurality N of sampling registers and including means for transferring in synchrony with said internal clock signal each said data word that has been held for at least one said internal clock interval in one said prolonged storage register to an associated one of said plurality of sampling registers;
• and
• multiplexer means coupled to said input bus and to said sampling register means for reassembling said data words in sequence at said input bus in synchrony with said internal clock signal.

A clock synchronizer system for transferring digital signals representing a plurality of data words including pad words from an output bus in an external clock domain operating in synchrony with an external clock signal having a frequency and an interval across an asynchronous boundary to an input bus in an internal clock domain operating in synchrony with an internal clock signal having a frequency and an interval, said system comprising:

• first register means for accepting and storing in turn each of a sequence of said data words from said output bus in synchrony with said external clock signal;
• clock divider means coupled to said external clock signal for producing, in synchrony with said external clock signal, a plurality of N of prolonged external clock signals each having an interval substantially equal to a plurality N of said external clock intervals;
• a plurality N of second register means each coupled to a corresponding one of said prolonged external clock signals, each said second register means being for storing said data word from said first register means, in synchrony with said one corresponding prolonged external clock signal, and each including valid flag means for setting a valid flag if said first register word is not an incoming pad word;
• a plurality N of third register means each having ready flag means for storing a ready flag and each coupled to said internal clock signal and a corresponding one of said second register means, said third register means being for storing said data word from said corresponding second register means when said ready flag is set;
• a plurality N of sampling means each coupled between said ready flag means in one of said third register means and said valid flag means in said corresponding second register means, each said sampling means being for setting said ready flag in said third register means associated with said each second register means in which said valid flag has been set for more than one said internal clock signal interval;
• and
• multiplexer means coupled to said plurality of third register means for connecting in sequence to said input bus, in synchrony with said internal clock signal, said data word from said each third register means in which said ready flag is set and for resetting said ready flag.

A synchronizing circuit for transferring digital signals representing a plurality of data words including pad words from an output bus in an external clock domain operating in synchrony with an external clock signal having a frequency and an interval across an asynchronous boundary to an input bus in an internal clock domain operating in synchrony with an internal clock signal having a frequency and an interval, said circuit comprising:

• a boundary register coupled to said output bus for storing each said data word in turn synchronously with said external clock signal;
• a clock divider coupled to said external clock signal for producing a plurality N of prolonged external clock signals each having an interval of substantially N said external clock intervals;
• a plurality N of external buffer registers coupled to said boundary register each having a valid flag and each coupled to and synchronized with an associated one of said prolonged external clock signals;
• a plurality N of internal buffer registers each having a ready flag and each synchronized to said internal clock signal and coupled to an associated one of said external buffer registers;
• a plurality N of flag sampling circuits synchronized with said internal clock signal, each coupled between an associated pair of said internal and external buffer registers for setting said ready flag after said valid flag has been set for more than one said internal clock interval;
• and
• a multiplexer coupled to said internal buffer registers for connecting in sequence to said input bus each said internal buffer register having said ready flag set including means for resetting said ready flag in said connected input buffer register.