Phase-based lock detector with programmable frequency offset tolerance

A circuit to compare a first clock signal with a second clock signal, the circuit comprising:

• synchronous elements to generate a first periodic signal phase dependent upon the first clock signal and a second periodic signal phase dependent upon the first clock signal and phase offset from the first periodic signal;
• a sampler coupled to the synchronous elements, the sampler to sample the first and second periodic signals timed to a sequence of edges of the second clock signal to produce a sequence of states, each state including concurrent samples of the first and second periodic signals;
• and
• a state machine coupled to the sampler to receive the sequence of states and sense a phase error between the first clock signal and the second clock signal responsive to a deviation of the sequence of states from an expected pattern of the states.

An integrated circuit comprising:

• a quadrature clock generator to generate orthogonal first and second periodic signals both phase dependent upon a first clock signal;
• a di-bit sampler coupled to the quadrature clock generator to sample the first and second periodic signals on edges of a second clock signal to produce a sequence of di-bit states, each di-bit state including concurrent samples of the first and second periodic signals;
• and
• a state machine coupled to the di-bit sampler to sense transitions between the di-bit states, the state machine to indicate an absence of frequency lock between the first and second clock signals if the transitions between the di-bit states deviate from a Gray-code sequence.