H03M 9/00
Parallel/series conversion or vice versa
Official title: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
H03M9/00 (Parallel/series conversion or vice versa) appears on 1,001 US grants and 704 published applications in this corpus.
Search patents in H03M- Granted patents
- 1,001
- Published applications
- 704
- Assignees
- 369
- Inventors
- 1,757
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 3 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 5 | 0 |
| 1984 | 5 | 0 |
| 1985 | 2 | 0 |
| 1986 | 4 | 0 |
| 1987 | 6 | 0 |
| 1988 | 3 | 0 |
| 1989 | 5 | 0 |
| 1990 | 6 | 0 |
| 1991 | 8 | 0 |
| 1992 | 9 | 0 |
| 1993 | 7 | 0 |
| 1994 | 12 | 0 |
| 1995 | 9 | 0 |
| 1996 | 13 | 0 |
| 1997 | 12 | 0 |
| 1998 | 22 | 0 |
| 1999 | 13 | 0 |
| 2000 | 20 | 0 |
| 2001 | 22 | 7 |
| 2002 | 21 | 11 |
| 2003 | 27 | 30 |
| 2004 | 29 | 21 |
| 2005 | 19 | 27 |
| 2006 | 39 | 30 |
| 2007 | 37 | 37 |
| 2008 | 33 | 46 |
| 2009 | 23 | 32 |
| 2010 | 43 | 26 |
| 2011 | 42 | 30 |
| 2012 | 35 | 31 |
| 2013 | 39 | 26 |
| 2014 | 37 | 30 |
| 2015 | 40 | 33 |
| 2016 | 40 | 30 |
| 2017 | 41 | 37 |
| 2018 | 38 | 25 |
| 2019 | 43 | 36 |
| 2020 | 38 | 32 |
| 2021 | 32 | 26 |
| 2022 | 33 | 22 |
| 2023 | 22 | 28 |
| 2024 | 28 | 13 |
| 2025 | 17 | 23 |
| 2026 | 13 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Encoding circuit, decoding circuit, encoding method, decoding method, and computer program4 Aug 2026US 12,700,874 B2NTT, Inc.
- Serdes lane control bonding systems and methods19 May 2026US 12,634,106 B2Lattice Semiconductor Corporation
- Dual loop for clock recovery in CDR14 Apr 2026US 12,603,752 B1Marvell Asia Pte Ltd
- Memory device including interface circuit and method of operating the same31 Mar 2026US 12,591,394 B2Samsung Electronics Co., Ltd.
- High speed, low power hybrid deserializer for chiplet-to-chiplet communication24 Mar 2026US 12,587,178 B1QUALCOMM Incorporated
- Power management in network devices8 Oct 2026US 2026/0310623 A1Cisco Technology, Inc.
- Data Link Layer Low Density Scramble Pattern27 Aug 2026US 2026/0254445 A1International Business Machines Corporation
- Low-latency word alignment for serdes interfaces using inline patterns30 Jul 2026US 2026/0219701 A1QUALCOMM Incorporated
- Memory device including interface circuit and method of operating the same23 Jul 2026US 2026/0211585 A1Samsung Electronics Co., Ltd.
- Data-dependent induced glitch mitigation for high-speed serializers18 Jun 2026US 2026/0169688 A1QUALCOMM Incorporated
Most cited
By later US patents
- System and method for transporting high-bandwidth signals over electrically conducting transmission lines185US 5,553,097 AInternational Business Machines Corporation · 1996
- System and method for sending multiple data signals over a serial link154US 5,835,498 ASilicon Image, Inc. · 1998
- High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines142US 6,160,423 AJazio, Inc. · 2000
- System and method for sending multiple data signals over a serial link123US 6,151,334 ASilicon Image, Inc. · 2000
- High speed parallel/serial link for data communication105US 6,222,380 B1International Business Machines Corporation · 2001