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US 6,222,380 B1Granted
High speed parallel/serial link for data communication
AssigneeInternational Business Machines Corporation
InventorsRobert Glen Gerowitz, Carl Thomas Gray, John Marshall, Christopher G. Riedle, Raymond Paul Rizzo
Life of this patent
Estimating the term…
Abstract
An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.
Claims25
An interface comprising:
- a plurality of latches that store a subset of a group of parallel bits;
- a system clock running at a predetermined speed that gates the bits into the plurality of latches;
- a multiplexer circuit, responsive to a control signal, that selects stored bits to generate a serial bit stream;
- a latch that receives the serial bit stream;
- a clock signal operating at N times the speed of the system clock operatively coupled to the latch;
- and
- a low power/impedance matching differential drive circuit that receives the serial bit stream from said latch and generates differential signals, with relatively high peak-to-peak signal swings.
4 more elements
An interface system comprising:
- at least one circuit arrangement partitioning parallel bits into subsets of parallel bits;
- a plurality of latches that store a subset of the parallel bits;
- a system clock operating at a predetermined speed that gates the bits into the latches;
- a multiplexer circuit, responsive to a control signal, that selects stored bits to generate a serial bit stream;
- a latch that receives the serial bit stream;
- a clock signal N times the speed of the system clock operatively coupled to the latch;
- and
- a low power/impedance matching differential drive circuit that receives the serial bit stream from the latch and generates differential signals with relatively high peak-to-peak signal swings.
5 more elements
A method for transmitting data comprising the steps of:
- partitioning the data into multiple groups of N parallel streams;
- generating one serial bit stream for each group of N parallel bit streams;
- providing a plurality of serial links;
- transmitting simultaneously each group of parallel bit streams over a different one of the plurality of said serial links;
- and
- transmitting, on at least one of the plurality of said serial links, training pattern of N-bits transition rich sequence prior to transmitting data on the at least one of the plurality of said serial links.
3 more elements
A system for transmitting data comprising:
- a multiplexer that partitions the data into multiple groups of N parallel bit streams;
- a converter that converts each one of the multiple groups of N parallel bit streams into one serial bit stream;
- a plurality of serial links wherein each one of the serial link transmits one of the serial bit stream containing the N parallel bit streams;
- and
- a pattern generator that generates a predetermined training pattern which is transmitted through at least one of the plurality of serial links prior to transmitting data through said at least one of the plurality of serial links.
2 more elements
An interface arrangement comprising:
- a plurality of latches that receives a subset of parallel bits from a group of parallel bits;
- a multiplexer circuit arrangement, response to a control signal, to generate a serial bit stream from the subset of parallel bits;
- a differential driver circuit responsive to the serial bit streams to generate differential signals to be transmitted via communications links;
- and
- a pattern generator that generates a training pattern that is transmitted by the communications links prior to transmitting the subset of parallel bits there through.
2 more elements
Dependencies are inferred from the claim text.