Data Link Layer Low Density Scramble Pattern

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a data link including a transmit side, the transmit side including:
• a physical layer circuit including a serial pin interface;
• a data link layer circuit coupled by one or more parallel multi-bit data lanes to the physical layer circuit, wherein the data link circuit transfers parallel data to the physical layer circuit responsive to a parallel clock signal, and wherein the data link layer circuit includes a data scrambling circuit including:
• a pseudo-random bit sequence generator circuit configured to generate, based on the parallel clock signal, a pseudo-random bit sequence having a width of M bits, wherein M is greater than 1;
• a hold circuit coupled to receive and hold the pseudo-random bit sequence for a selected number of cycles of the parallel clock signal determined by a hold signal;
• and
• a timing circuit configured to assert the hold signal based on multiple cycles of the parallel clock signal.

A method of handling data at a transmit side of a data link, the method comprising:

• at a data link layer circuit:
• generating, based on a parallel clock signal, a pseudo-random bit sequence having a width of M bits, wherein M is greater than 1;
• holding the pseudo-random bit sequence for a selected number of cycles of the parallel clock signal determined by a hold signal;
• asserting, by a timing circuit, the hold signal based on multiple cycles of the parallel clock signal;
• transferring data from the data link layer circuit to a physical layer circuit via one or more parallel multi-bit data lanes responsive to the parallel clock signal;
• and
• transmitting the data, by the physical layer circuit, via a serial pin interface.