High speed, low power hybrid deserializer for chiplet-to-chiplet communication

A method for configuring a data conversion circuit, comprising:

• selecting a mode of operation for the data conversion circuit based on frequency of a clock signal that controls a rate at which data is to be shifted through the data conversion circuit;
• enabling first cascaded flipflops to convert first data to second data in a first mode of operation, the first cascaded flipflops comprising a plurality of series-coupled dynamic flipflops, each dynamic flipflop being configured to retain signaling state of its output based on a capacitance at its input;
• configuring a first selection circuit to select an output of the first cascaded flipflops as an output of the data conversion circuit in the first mode of operation;
• enabling second cascaded flipflops to convert the first data to the second data in a second mode of operation, the second cascaded flipflops comprising a plurality of series-coupled static flipflops, each static flipflop being configured to retain signaling state of its output through a feedback circuit that actively drives its input;
• and
• configuring the first selection circuit to select an output of the second cascaded flipflops as the output of the data conversion circuit in the second mode of operation.

An apparatus, comprising:

• means for selecting between first cascaded flipflops and second cascaded flipflops to convert first data to second data;
• and
• means for selecting an output of a data conversion circuit from an output of the first cascaded flipflops and an output of the second cascaded flipflops,
• wherein the first cascaded flipflops comprises a plurality of series-coupled dynamic flipflops, each dynamic flipflop being configured to retain signaling state of its output based on a capacitance at its input,
• wherein the second cascaded flipflops comprises a plurality of series-coupled static flipflops, each static flipflop being configured to retain signaling state of its output through a feedback circuit that actively drives its input, and
• wherein the means for selecting between first cascaded flipflops and second cascaded flipflops and the means for selecting the output of a data conversion circuit are controlled by a signal indicating frequency of a clock signal that controls a rate at which data is to be shifted through the data conversion circuit.