Data-dependent induced glitch mitigation for high-speed serializers

An apparatus comprising:

• means for capturing data bits from a plurality of datastreams during each cycle of a clock signal;
• and
• means for transmitting the data bits in sequential bit transmission intervals through a first output of the apparatus,
• wherein the means for transmitting the data bits is configured to respond to a delayed version of the clock signal, and
• wherein the data bits are captured from a first data signal that encodes a bitstream comprising even bits of a first parallel data element and a second data signal that encodes a bitstream comprising odd bits of the first parallel data element.

A method for serializing data, comprising:

• capturing first data bits from a first data signal during each cycle of a clock signal, the first data signal encoding a bitstream comprising even bits of a parallel data element;
• capturing second data bits from a second data signal during each cycle of the clock signal, the second data signal encoding a bitstream comprising odd bits of the parallel data element;
• providing the clock signal as an input to a delay circuit comprising one or more series-coupled inverters;
• and
• multiplexing the first data bits and the second data bits into an output signal in accordance with timing provided by a delayed clock signal output by the delay circuit.