H03M 13/1125
Using different domains for check node and bit node processing, wherein the
Official title: {using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs}
H03M13/1125 (Using different domains for check node and bit node processing, wherein the) appears on 165 US grants and 173 published applications in this corpus.
Search patents in H03M- Granted patents
- 165
- Published applications
- 173
- Assignees
- 88
- Inventors
- 355
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2003 | 0 | 1 |
| 2004 | 0 | 0 |
| 2005 | 1 | 3 |
| 2006 | 0 | 1 |
| 2007 | 1 | 4 |
| 2008 | 1 | 2 |
| 2009 | 1 | 2 |
| 2010 | 5 | 1 |
| 2011 | 1 | 4 |
| 2012 | 3 | 4 |
| 2013 | 6 | 5 |
| 2014 | 10 | 9 |
| 2015 | 9 | 8 |
| 2016 | 5 | 3 |
| 2017 | 7 | 7 |
| 2018 | 4 | 12 |
| 2019 | 19 | 19 |
| 2020 | 16 | 18 |
| 2021 | 15 | 8 |
| 2022 | 8 | 5 |
| 2023 | 9 | 16 |
| 2024 | 20 | 10 |
| 2025 | 15 | 23 |
| 2026 | 9 | 8 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- LDPC encoding and decoding method and related apparatus29 Sep 2026US 12,750,069 B2Huawei Technologies Co., Ltd.
- Receiver for adjusting log likelihood ratio and method of operating the same8 Sep 2026US 12,732,212 B2Samsung Electronics Co., Ltd.
- Iterative error decoding with early termination of decoding process11 Aug 2026US 12,706,615 B2Micron Technology, Inc.
- Encoding circuit, decoding circuit, encoding method, decoding method, and computer program4 Aug 2026US 12,700,874 B2NTT, Inc.
- Error decoding with iterative parameter updating14 Jul 2026US 12,683,630 B2Micron Technology, Inc.
- Decoder scheme capable of reducing frequency of memory reading and writing during iterative decoding procedure24 Sep 2026US 2026/0291523 A1Silicon Motion, Inc.
- Ranked successive detection and decoding method and receiver based on sparse code multiple access17 Sep 2026US 2026/0280586 A1Guangdong University of Technology
- Learning-based min-sum hard decoding for non-volatile memory devices4 Jun 2026US 2026/0155836 A1
- Systems and methods for concurrent decoding of product lifted low density parity check (ldpc) codes16 Apr 2026US 2026/0106632 A1Avago Technologies International Sales Pte. Limited
- Communication devices and methods26 Mar 2026US 2026/0088937 A1Sony Group Corporation
Most cited
By later US patents
- Reduced-complexity decoding of parity check codes161US 7,752,523 B1Marvell International Ltd. · 2010
- Node processors for use in parity check decoders93US 6,938,196 B2Flarion Technologies, Inc. · 2005
- Read retry operations where likelihood value assignments change sign at different read voltages for each read retry44US 9,633,740 B1Seagate Technology LLC · 2017
- Node processors for use in parity check decoders15US 7,673,223 B2QUALCOMM Incorporated · 2010
- Variable barrel shifter15US 8,707,123 B2LSI Corporation · 2014