Node processors for use in parity check decoders
AssigneeFlarion Technologies, Inc.
InventorsTom Richardson, Vladimir Novichkov
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AssigneeFlarion Technologies, Inc.
InventorsTom Richardson, Vladimir Novichkov
Estimating the term…
Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages. The delay pipeline includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.
A decoder processing method, comprising:
A message passing decoder method, the method comprising the steps of:
A device for processing detected values, the device comprising:
A device for performing node processing operations as part of a message passing decoding process, the device comprising:
A node processor for use in a message passing decoding system, the node processor including:
A method of performing node processing operations in a message passing decoder, the method comprising the steps of:
Dependencies are inferred from the claim text.