US 2026/0155836 A1 · LEARNING-BASED MIN-SUM HARD DECODING FOR NON-VOLATILE MEMORY DEVICES

Abstract

Methods and systems for improving performance of a decoder in a memory device are described. An example method includes receiving a noisy codeword, generating, based on the noisy codeword, a first log likelihood ratio (LLR) sequence that uses symmetric LLR metrics, and performing, on a second LLR sequence, a decoding iteration to generate a decoded data sequence. Upon determining that a checksum of the decoded data sequence satisfies a condition, the method further includes generating, based on the decoded data sequence, an intermediate sequence, incrementing at least one of multiple counters based on comparing corresponding bits of the intermediate sequence and the noisy codeword, and updating, based on the multiple counters, the second LLR sequence, which is used to perform another decoding iteration. An example system implements the above-described method using one or more processors.

Claims20

Dependent claims

A method of improving a performance of a decoder in a memory device, comprising:

(a) receiving, from at least one memory cell of the memory device, a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
(b) generating, based on the noisy codeword, a first log likelihood ratio (LLR) sequence that uses symmetric LLR metrics;
(c) performing, on a second LLR sequence, a decoding iteration to generate a decoded data sequence, wherein the second LLR sequence is based on the first LLR sequence;
upon determining that a checksum of the decoded data sequence satisfies a condition indicative of the noisy codeword not being successfully decoded,
(d) generating, based on the decoded data sequence, an intermediate sequence;
(e) incrementing at least one of a first counter (B_00), a second counter (B_01), a third counter (B_10), or a fourth counter (B_11) based on comparing corresponding bits of the intermediate sequence and the noisy codeword;
and
(f) updating, based on the first counter, the second counter, the third counter, and the fourth counter, the second LLR sequence;
and
(g) repeating operations (c) through (f) until the noisy codeword is successfully decoded or an index of the decoding iteration has exceeded a maximum number of decoding iterations.

7 more elements

A system for improving a performance of a decoder in a memory device, comprising:

one or more processors and a memory including instructions stored thereupon, wherein the instructions upon execution by the one or more processors cause the one or more processors to:
(a) receive, from at least one memory cell of the memory device, a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
(b) generate, based on the noisy codeword, a first log likelihood ratio (LLR) sequence that uses symmetric LLR metrics;
(c) perform, on a second LLR sequence, a decoding iteration to generate a decoded data sequence, wherein the second LLR sequence is based on the first LLR sequence;
upon determining that a checksum of the decoded data sequence satisfies a condition indicative of the noisy codeword not being successfully decoded,
(d) generate, based on the decoded data sequence, an intermediate sequence;
(e) increment at least one of a first counter (B_00), a second counter (B_01), a third counter (B_10), or a fourth counter (B_11) based on comparing corresponding bits of the intermediate sequence and the noisy codeword;
and
(f) update, based on the first counter, the second counter, the third counter, and the fourth counter, the second LLR sequence;
and
(g) repeat operations (c) through (f) until the noisy codeword is successfully decoded or an index of the decoding iteration has exceeded a maximum number of decoding iterations.

8 more elements

A non-transitory computer-readable storage medium having instructions stored thereupon for improving a performance of a decoder in a memory device, comprising:

(a) instructions for receiving, from at least one memory cell of the memory device, a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
(b) instructions for generating, based on the noisy codeword, a first log likelihood ratio (LLR) sequence that uses symmetric LLR metrics;
(c) instructions for performing, on a second LLR sequence, a decoding iteration to generate a decoded data sequence, wherein the second LLR sequence is based on the first LLR sequence;
upon determining that a checksum of the decoded data sequence satisfies a condition indicative of the noisy codeword not being successfully decoded,
(d) instructions for generating, based on the decoded data sequence, an intermediate sequence;
(e) instructions for incrementing at least one of a first counter (B_00), a second counter (B_01), a third counter (B_10), or a fourth counter (B_11) based on comparing corresponding bits of the intermediate sequence and the noisy codeword;
and
(f) instructions for updating, based on the first counter, the second counter, the third counter, and the fourth counter, the second LLR sequence;
and
(g) instructions for repeating operations (c) through (f) until the noisy codeword is successfully decoded or an index of the decoding iteration has exceeded a maximum number of decoding iterations.

7 more elements

Dependencies are inferred from the claim text.

Learning-based min-sum hard decoding for non-volatile memory devices

Life of this patent

Learning-based min-sum hard decoding for non-volatile memory devices

Life of this patent

Abstract

Claims20