Error decoding with iterative parameter updating
AssigneeMicron Technology, Inc.
InventorsMustafa N. Kaynak, Mariano Burich, Sivagnanam Parthasarathy, Eyal En Gad
Life of this patent
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Abstract
An error-handling module of a controller determines that a codeword received from a memory device has errors. The error-handing module assigs an initial set of log-likelihood ratios (LLRs) to bits of the codeword based on a column weight (CW) of a low density parity check (LDPC) code. The error-handling module updates the LLRs based on parity check outcomes. The controller decodes embedded data from the codeword based on the updated LLRs.
Claims17
A method for decoding data, comprising:
- determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
- assigning, by the error-handling module responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) of each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
- responsive to the assigning, iteratively updating, by the error-handling module, the LLRs based on parity check outcomes;
- and
- decoding, by the controller, embedded data from the codeword based on the updated LLRs.
A system for decoding data stored in a memory device, comprising:
- a memory device;
- and
- a processing device coupled to the memory, the processing device to perform operations comprising:
- determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
- assigning, responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
- responsive to the assigning, iteratively updating the LLRs based on parity check outcomes;
- and
- decoding embedded data from the codeword based on the updated LLRs.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
- assigning, by the error-handling module responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) of each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
- responsive to the assigning, iteratively updating, by the error-handling module, the LLRs based on parity check outcomes;
- and
- decoding, by the controller, data from the codeword based on the updated LLRs.
Dependencies are inferred from the claim text.