H03L 7/191
Using at least two different signals from the frequency divider or the
Official title: using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence)
H03L7/191 (Using at least two different signals from the frequency divider or the) appears on 137 US grants and 64 published applications in this corpus.
Search patents in H03L- Granted patents
- 137
- Published applications
- 64
- Assignees
- 87
- Inventors
- 212
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 3 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 2 | 0 |
| 1984 | 1 | 0 |
| 1985 | 2 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 4 | 0 |
| 1994 | 5 | 0 |
| 1995 | 5 | 0 |
| 1996 | 3 | 0 |
| 1997 | 3 | 0 |
| 1998 | 6 | 0 |
| 1999 | 4 | 0 |
| 2000 | 9 | 0 |
| 2001 | 8 | 3 |
| 2002 | 4 | 7 |
| 2003 | 3 | 1 |
| 2004 | 1 | 4 |
| 2005 | 8 | 5 |
| 2006 | 1 | 3 |
| 2007 | 2 | 1 |
| 2008 | 1 | 0 |
| 2009 | 1 | 2 |
| 2010 | 3 | 1 |
| 2011 | 0 | 3 |
| 2012 | 4 | 0 |
| 2013 | 1 | 2 |
| 2014 | 1 | 0 |
| 2015 | 0 | 1 |
| 2016 | 0 | 0 |
| 2017 | 0 | 2 |
| 2018 | 2 | 4 |
| 2019 | 9 | 10 |
| 2020 | 6 | 3 |
| 2021 | 8 | 1 |
| 2022 | 3 | 3 |
| 2023 | 0 | 1 |
| 2024 | 3 | 3 |
| 2025 | 2 | 2 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Phase detection circuit, and clock generation circuit and method using the same16 Jun 2026US 12,658,929 B2SK hynix Inc.
- Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information2 Jun 2026US 12,645,248 B2SK hynix Inc.
- Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component23 Sep 2025US 12,425,011 B2Teledyne E2V Semiconductors SAS
- Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device25 Mar 2025US 12,261,613 B2Micron Technology, Inc.
- Phase estimation for high frequency signals23 Jul 2024US 12,047,084 B1International Business Machines Corporation
- Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information10 Sep 2026US 2026/0267370 A1SK hynix Inc.
- Phase detection circuit, and clock generation circuit and method using the same15 Jan 2026US 2026/0019086 A1SK hynix Inc.
- Synchronization of frequency divided reference clocks18 Sep 2025US 2025/0293698 A1Space Exploration Technologies Corp.
- Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information13 Feb 2025US 2025/0053189 A1SK hynix Inc.
- Phase estimation for high frequency signals4 Jul 2024US 2024/0223195 A1International Business Machines Corporation
Most cited
By later US patents
- Clock and data recovery PLL based on parallel architecture104US 6,211,741 B1Cypress Semiconductor Corporation · 2001
- Voltage controlled oscillator operating with digital controlled loads in a phase lock loop102US 5,304,955 AMotorola, Inc. · 1994
- Phase-locked loop circuit73US 4,888,564 AVictor Company of Japan, Ltd. · 1989
- Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop70US 5,550,515 AOPTi Inc. · 1996
- Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications62US 6,147,567 ASilicon Laboratories Inc. · 2000