Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device

A memory device, comprising:

• a first die, comprising:
• a first plurality of memory cells;
• and
• division circuitry configured to:
• receive a clock;
• generate a divided clock having a lower frequency than that of the clock;
• and
• generate a plurality of component clocks based on the divided clock;
• and
• a plurality of transmitters configured to transmit the plurality of component clocks using a plurality of inter-die interconnects between the first die and a second die, wherein the first die comprises a primary memory die clock reconstruction circuitry that is inactive during operation of the memory device;
• and
• the second die, comprising:
• a plurality of receivers configured to receive the plurality of component clocks;
• and
• clock reconstruction circuitry configured to reconstruct the divided clock from the plurality of component clocks.

A method, comprising:

• at a primary memory die of a three-dimensional stack of a memory device, dividing a received clock to generate a divided clock;
• in the primary memory die, generating a plurality of component clocks based on the divided clock;
• transmitting the plurality of component clocks from the primary memory die to one or more internal memory die in the three-dimensional stack of the memory device using inter-die interconnects;
• at the one or more internal memory die of the three-dimensional stack, receiving the plurality of component clocks from the primary memory die over the inter-die interconnects;
• and
• in the one or more internal memory die, reconstructing the divided clock from the received plurality of component clocks.