Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop

Phase-locked loop apparatus for producing an output signal having an output signal frequency, in response to an input signal oscillating at an input signal frequency, each cycle of said input signal being divided into a plurality of phase intervals, comprising:

• preliminary circuitry having an input coupled to receive said input signal and further having M outputs, M>1, said preliminary circuitry producing a respective reference signal on each of said outputs, each of said reference signals being a delayed version of said input signal and each i'th one of said reference signals being delayed by a respective i'th different delay time relative to a 0'th one of said reference signals, 0<i<M, all of said delay times being positive but shorter than one period of said input signal frequency;
• M phase detectors, each having a reference input, a feedback input and an output, the reference input of each of said phase detectors being coupled to receive a respective one of said reference signals and the feedback input of each of said phase detectors being coupled to receive a respective one of M feedback signals;
• output frequency control circuitry having M inputs each coupled to the output of a respective one of said phase detectors, said output frequency control circuitry further having an output;
• a controlled oscillator having a control input coupled to the output of said output frequency control circuitry and further having an output carrying said output signal of said phase-locked loop apparatus;
• and
• feedback circuitry, responsive to the output of said output frequency control circuitry, having M outputs each carrying a respective one of said feedback signals, each of said respective feedback signals having a frequency of (1/N) times said output signal frequency, where N is programmable, and each of said feedback signals being delayed by a respective j'th different delay time relative to a 0'th one of said feedback signals, 0<j<M, all of said delay times being positive but shorter than N times one period of said output signal frequency.

An improved phase-locked loop, comprising:

• a preliminary phase-locked loop having an input connected to an input signal source, the preliminary phase-locked loop having M outputs, where M is a number greater than one;
• a number M of phase detectors, each having a first input connected to a respective one of the outputs of the preliminary phase-locked loop, said phase detectors each further having a second input and an output;
• a number M of charge pumps, each having an input connected to the output of a respective one of the phase detectors;
• a low-pass filter having an input port connected to the outputs of all of the phase detectors, said filter further having an output;
• a voltage-controlled oscillator having a control input connected to the output of the low-pass filter, wherein the voltage-controlled oscillator has at least one output;
• a divide-by-N feedback frequency divider, having an input port connected to the at least one output of the voltage-controlled oscillator, and having M outputs, each output of the feedback frequency divider being connected to the second input of a respective one of the phase detectors, N being a non-integer multiple of M.

A method for generating a system output signal having an output frequency and a phase, in response to an input signal having a phase and an input frequency, the system output signal having an output frequency of a predetermined number N times said input frequency, said method comprising the steps of:

• producing a plurality of reference signals responsive to said input signal, each having a different respective phase relative to that of the input signal and a respective frequency related to the input frequency;
• producing a plurality of feedback signals, each of said feedback signals having a different respective phase relative to that of the output signal and a feedback frequency having a relation to the output frequency, each of said feedback signals corresponding to a respective one of said reference signals;
• programming said relation of said feedback frequency to said output frequency;
• producing a plurality of error signals, each responsive to the difference between the phase of a respective one of the reference signals and that of its corresponding feedback signal;
• and
• adjusting the frequency of the system output signal in response to at least two of the plurality of error signals.

An improved phase-locked loop, for use with an input signal having a frequency and a phase, comprising:

• a preliminary phase-locked loop which accepts the input signal and produces four reference signals, each reference signal having a common frequency related to the frequency of the input signal, first, second and third ones of the reference signals further having phases of 90.degree., 180.degree. and 270.degree., respectively, relative to a 0'th one of the reference signals;
• four phase detectors, each associated with a respective one of the reference signals and with a respective one of four feedback signals, each of said four feedback signals having a frequency and a phase, the frequencies of the feedback signals being equal and the phases of first, second and third ones of the feedback signals being 90.degree., 180.degree. and 270.degree., respectively, from the phase of a 0'th one of the feedback signals, each phase detector accepting its associated reference signal and feedback signal and producing a respective error signal in response to the difference between the phase of its associated reference signal and its associated feedback signal;
• four charge pumps, each of said four charge pumps accepting one of said error signals produced by one of the four phase detectors and producing a respective current output, the outputs of said four charge pumps being current-summed to produce a system error signal;
• a voltage-controlled oscillator, connected to receive system error signal, said voltage-controlled oscillator producing an output signal and four intermediate signals, each of the output signals and four intermediate signals having a frequency and a phase, the frequencies of the output signal and all four intermediate signals being equal and the phase of first, second and third ones of the intermediate signals being 90.degree., 180.degree. and 270.degree., respectively, from the phase of a 0'th one of the intermediate signals, the frequency of the four intermediate signals being determined in response to the system error signal;
• and
• a divide-by-N frequency divider, accepting the four intermediate signals and producing said feedback signals, the frequency and phase of the feedback signals being related to the frequency and phase of said intermediate signals, where N is a non-integer multiple of four.

Phase-locked loop apparatus for producing an output signal having an output signal frequency, in response to an input signal oscillating at an input signal frequency, each cycle of said input signal being divided into a plurality of phase intervals, comprising:

• preliminary circuitry having an input coupled to receive said input signal and further having M outputs, M>1, said preliminary circuitry producing a respective reference signal on each of said outputs, each of said reference signals being a delayed version of said input signal and each i'th one of said reference signals being delayed by a respective i'th different delay time relative to a O'th one of said reference signals, O<i<M, all of said delay times being positive but shorter than one period of said input signal frequency;
• M phase detectors, each having a reference input, a feedback input and an output, the reference input of each of said phase detectors being coupled to receive a respective one of said reference signals and the feedback input of each of said phase detectors being coupled to receive a respective one of M feedback signals;
• output frequency control circuitry having M inputs each coupled to the output of a respective one of said phase detectors, said output frequency control circuitry further having an output;
• a controlled oscillator having a control input coupled to the output of said output frequency control circuitry and further having an output carrying said output signal of said phase-locked loop apparatus;
• and
• feedback circuitry, responsive to the output of said output frequency control circuitry, having M outputs each carrying a respective one of said feedback signals and comprising:
• M divide-by-N frequency dividers each having an input coupled to receive a respective intermediate signal oscillating with a frequency responsive to said output of said output frequency control circuitry, and further having an output carrying a respective one of said feedback signals;
• and
• (M-1) delay elements, each j'th delay element including means for preventing a corresponding j'th one of said frequency dividers from starting for (j/M).multidot.N cycles of one of said intermediate signals, relative to a start time of a 0'th one of said frequency dividers, 0<j<M.