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US 2025/0053189 A1Published application
Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information
AssigneeSK hynix Inc.
InventorJi Hyo KANG
Life of this patent
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Abstract
A semiconductor apparatus includes a frequency control circuit and an internal clock generation circuit. The frequency control circuit generates a frequency information signal based on a command address signal, and generates a frequency control signal by comparing the frequency information signal with a frequency setting signal. The internal clock generation circuit generates an internal clock signal from a system clock signal based on the frequency control signal.
Claims31
A semiconductor apparatus comprising:
- a frequency detector configured to generate a frequency information signal based on a command address signal;
- a first frequency control signal generator configured to compare a first frequency setting signal with the frequency information signal to generate a first frequency control signal;
- a second frequency control signal generator configured to compare a second frequency setting signal with the frequency information signal to generate a second frequency control signal;
- and
- an internal clock generation circuit configured to generate an internal clock signal from a system clock signal based on the first and second frequency control signals.
2 more elements
A semiconductor apparatus comprising:
- a frequency control circuit configured to generate a frequency information signal based on a command address signal and configured to compare a first frequency setting signal with the frequency information to generate a first frequency control signal;
- and
- a clock receiver configured to receive a system clock signal to generate a received clock signal, to increase an alternating current (AC) gain of the clock receiver when the first frequency control signal is enabled, and to increase a direct current (DC) gain of the clock receiver when the first frequency control signal is disabled.
A semiconductor apparatus comprising:
- a frequency control circuit configured to generate a frequency information signal based on a command address signal and configured to compare a first frequency setting signal with the frequency information signal to generate a first frequency control signal;
- a clock receiver configured to receive a system clock signal to generate a received clock signal;
- a first clock path configured to buffer the received clock signal at a current mode logic (CML) level to generate a first differential clock signal pair when the first frequency control signal is enabled;
- and
- a second clock path configured to buffer the received clock signal at a complementary metal-oxide-semiconductor (CMOS) level to generate a second differential clock signal pair by when the first frequency control signal is disabled.
2 more elements
Dependencies are inferred from the claim text.