Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component

A method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), the first clock signal (CK1) and the second clock signal (CK2) being generated synchronously and having an identical clock period (Tc), comprising the steps of:

• S10) transmitting by means of the first electronic component (CE1) a first calibration signal (S12) synchronously with the first clock signal (CK1);
• S20) measuring a first delay (T1) between an active edge of the first calibration signal (S12) and an active edge of the second clock signal (CK2) consecutive to the active edge of the first calibration signal (S12);
• S30) transmitting by means of the second electronic component (CE2) a second calibration signal (S21) synchronously with the second clock signal (CK2);
• S40) measuring a second delay (T2) between an active edge of the second calibration signal (S21) and an active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21);
• S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21), the number (n) of clock pulses corresponding to a multiple of the clock period (Tc);
• S60) determining the phase difference depending on the parity of the number (n) of clock pulses.