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US 6,211,741 B1Granted
Clock and data recovery PLL based on parallel architecture
AssigneeCypress Semiconductor Corporation
InventorKamal Dalmia
Life of this patent
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Abstract
An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.
Claims14
An apparatus comprising:
- a first circuit configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal;
- and
- a clock circuit configured to generate said first and second clock signals in response to said output signal, wherein said clock circuit comprises (i) an N-rate VCO configured to generate N-subclocks and (ii) N/2 gates configured to generate said first and second clocks in response to said N-subclocks.
An apparatus comprising:
- means for generating an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal;
- and
- means for generating said first and second clock signals in response to said output signal, wherein means for generating said first and second clock signals comprises (i) an N-rate VCO configured to generate N-subclocks and (ii) N/2 gates configured to generate said first and second clocks in response to said N-subclocks.
A method for clock and data recovery comprising the steps of:
- (A) generating an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal;
- (B) generating N-subclocks;
- and
- (C) generating said first and second clock signals in response to said output signal and said N-subclocks.
1 more element
Dependencies are inferred from the claim text.