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US 12,658,929 B2Granted
Phase detection circuit, and clock generation circuit and method using the same
AssigneeSK hynix Inc.
InventorHan Sol Na
Life of this patent
Estimating the term…
Abstract
A clock generation circuit performs a delay-locked operation on a reference clock signal. The clock generation circuit is configured to perform the delay-locked operation by comparing the phases of a division reference clock signal and a feedback clock signal. After the delay-locked operation is completed, the clock generation circuit is configured to selectively invert the phase of the division reference clock signal by comparing the phases of the division reference clock signal and the delay feedback clock signal.
Claims20
A phase detection circuit comprising:
- a division circuit configured to generate a first division clock signal and a second division clock signal by dividing a reference clock signal;
- a clock selection circuit configured to output one of the first and second division clock signals as a division reference clock signal based on an edge detection signal;
- a phase detector group configured to generate a phase detection signal by comparing phases of the division reference clock signal and a feedback clock signal;
- and
- an edge detector configured to generate the edge detection signal by comparing a phase of a delay feedback clock signal that is generated by delaying the feedback clock signal and the phase of the division reference clock signal.
2 more elements
A clock generation circuit comprising:
- a delay line configured to generate a delay clock signal by delaying a reference clock signal based on a first delay control signal and a second delay control signal;
- a first division circuit configured to generate an output clock signal by dividing a frequency of the delay clock signal;
- a second division circuit configured to generate a division output clock signal by dividing a frequency of the output clock signal;
- a delay model circuit configured to generate a feedback clock signal by delaying the division output clock signal by a modeled delay time;
- a phase detection circuit configured to generate a division reference clock signal by dividing the reference clock signal, to generate a first phase detection signal by comparing phases of the division reference clock signal and the feedback clock signal during a first delay-locked operation, to generate a second phase detection signal by comparing the phases of the division reference clock signal and the feedback clock signal during a second delay-locked operation, and to selectively invert the phase of the division reference clock signal based on the division reference clock signal and the feedback clock signal after the first delay-locked operation is completed;
- and
- a delay control circuit configured to generate the first delay control signal based on the first phase detection signal and configured to generate the second delay control signal based on the second phase detection signal.
4 more elements
A clock generation method comprising:
- generating a division reference clock signal by dividing a reference clock signal;
- performing a first delay-locked operation by delaying a phase of the reference clock signal by comparing phases of the division reference clock signal and a feedback clock signal;
- and
- selectively inverting, when the first delay-locked operation is completed, the phase of the division reference clock signal by comparing a phase of a delay feedback clock signal, which is generated by delaying the feedback clock signal, and the phase of the division reference clock signal.
1 more element
Dependencies are inferred from the claim text.