H03K 19/17708
Using an and matrix followed by an or matrix, i.e. programmable logic
Official title: {using an AND matrix followed by an OR matrix, i.e. programmable logic arrays}
H03K19/17708 (Using an and matrix followed by an or matrix, i.e. programmable logic) appears on 477 US grants and 123 published applications in this corpus.
Search patents in H03K- Granted patents
- 477
- Published applications
- 123
- Assignees
- 159
- Inventors
- 694
- Latest grant
- 30 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 7 | 0 |
| 1977 | 8 | 0 |
| 1978 | 5 | 0 |
| 1979 | 2 | 0 |
| 1980 | 6 | 0 |
| 1981 | 3 | 0 |
| 1982 | 5 | 0 |
| 1983 | 11 | 0 |
| 1984 | 10 | 0 |
| 1985 | 21 | 0 |
| 1986 | 8 | 0 |
| 1987 | 20 | 0 |
| 1988 | 23 | 0 |
| 1989 | 32 | 0 |
| 1990 | 29 | 0 |
| 1991 | 32 | 0 |
| 1992 | 20 | 0 |
| 1993 | 16 | 0 |
| 1994 | 10 | 0 |
| 1995 | 12 | 0 |
| 1996 | 12 | 0 |
| 1997 | 8 | 0 |
| 1998 | 8 | 0 |
| 1999 | 6 | 0 |
| 2000 | 4 | 0 |
| 2001 | 9 | 0 |
| 2002 | 8 | 12 |
| 2003 | 3 | 3 |
| 2004 | 7 | 2 |
| 2005 | 4 | 4 |
| 2006 | 6 | 5 |
| 2007 | 6 | 2 |
| 2008 | 2 | 2 |
| 2009 | 4 | 0 |
| 2010 | 1 | 1 |
| 2011 | 1 | 1 |
| 2012 | 1 | 3 |
| 2013 | 1 | 2 |
| 2014 | 8 | 8 |
| 2015 | 5 | 1 |
| 2016 | 6 | 6 |
| 2017 | 9 | 8 |
| 2018 | 9 | 5 |
| 2019 | 14 | 11 |
| 2020 | 14 | 10 |
| 2021 | 7 | 6 |
| 2022 | 7 | 12 |
| 2023 | 11 | 6 |
| 2024 | 5 | 3 |
| 2025 | 6 | 9 |
| 2026 | 5 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Processing method, asynchronous circuit, and logic circuit30 Jun 2026US 12,671,419 B2Sony Semiconductor Solutions Corporation
- Sectional configuration for programmable logic devices2 Jun 2026US 12,647,118 B2QuickLogic Corporation
- Reconfigurable array for analog applications24 Feb 2026US 12,562,743 B2Drexel University
- Active capacitive shield for programmable logic array27 Jan 2026US 12,537,528 B2STMicroelectronics International N. V.
- Capacitance sensor array chip with programmable fusion pixels, sampling device thereof and controlling system thereof6 Jan 2026US 12,519,473 B2National Yang Ming.Chiao Tung University
- Digital Signal Processing (DSP) Block with Systolic Filter Support Circuitry25 Jun 2026US 2026/0178277 A1Altera Corporation
- Capacitance sensor array chip with programmable fusion pixels, sampling device thereof and controlling system thereof20 Nov 2025US 2025/0357930 A1National Yang Ming.Chiao Tung University
- Logic drive based on multichip package using interconnection bridge28 Aug 2025US 2025/0273625 A1iCometrue Company Ltd.
- Logic drive based on chip scale package comprising standardized commodity programmable logic ic chip and memory ic chip7 Aug 2025US 2025/0253290 A1iCometrue Company Ltd.
- Active capacitive shield for programmable logic array7 Aug 2025US 2025/0253852 A1STMicroelectronics International N. V.
Most cited
By later US patents
- Programmable logic array device using EPROM technology377US 4,609,986 AAltera Corporation · 1986
- Programmable logic array device using EPROM technology330US 4,617,479 AAltera Corporation · 1986
- Registered logic macrocell with product term allocation and adjacent product term stealing244US 5,121,006 AAltera Corporation · 1992
- Programmable logic storage element for programmable logic devices241US 4,677,318 AAltera Corporation · 1987
- Programmable array logic circuit196US 4,124,899 AMonolithic Memories, Inc. · 1978