Logic drive based on multichip package using interconnection bridge

A multi-chip package comprising:

• a plurality of interconnection bridges at a same horizontal level and each comprising a silicon substrate and a first interconnection scheme over the silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers, wherein the first interconnection metal layer comprises a first copper layer and a first adhesion metal layer at a bottom and sidewall of the first copper layer;
• a first polymer layer at the same horizontal level as the plurality of interconnection bridges and having a portion in a gap between two of the plurality of interconnection bridges;
• a plurality of vertical metal interconnects in the first polymer layer and at the same horizontal level as the plurality of interconnection bridges and the first polymer layer;
• a second interconnection scheme over the plurality of interconnection bridges, the first polymer layer and the plurality of vertical metal interconnects, wherein the second interconnection scheme comprises a second polymer layer at a top of the second interconnection scheme and a plurality of metal pads each having a first portion in an opening in the second polymer layer and a second portion over the opening in the second polymer layer and on a top surface of the second polymer layer, wherein the plurality of metal pads comprise a first and a second metal pad vertically over and coupling to a first interconnection bridge of the plurality of interconnection bridges and a third and a fourth metal pad vertically over and coupling to a second interconnection bridge of the plurality of interconnection bridges;
• a plurality of first metal bumps at a bottom of the multi-chip package, wherein a first one of the plurality of first metal bumps couples to the second interconnection scheme through a first vertical metal interconnect of the plurality of vertical metal interconnects, wherein each of the plurality of first metal bumps comprises tin;
• a plurality of semiconductor chips over the second interconnection scheme, wherein the plurality of semiconductor chips comprise a first semiconductor chip extending across a first edge of the first interconnection bridge and a second semiconductor chip extending across a first edge of the second interconnection bridge, wherein the first semiconductor chip comprises a plurality of second metal bumps at its bottom and having a first one bonded to the first metal pad and coupling to the first interconnection bridge, and wherein the second semiconductor chip comprises a plurality of third metal bumps at its bottom and having one bonded to the third metal pad and coupling to the second interconnection bridge, wherein each of the first and second semiconductor chips is a logic chip;
• a plurality of memory modules over the second interconnection scheme, wherein the plurality of memory modules comprise a first memory module extending across a second edge of the first interconnection bridge and a second memory module extending across a second edge of the second interconnection bridge, wherein the first memory module comprises a plurality of fourth metal bumps at its bottom and having a first one bonded to the second metal pad and coupling to the first interconnection bridge, wherein the second memory module comprises a plurality of fifth metal bumps at its bottom and having one bonded to the fourth metal pad and coupling to the second interconnection bridge, wherein the first one of the plurality of fourth metal bumps of the first memory module couples to the first one of the plurality of second metal bumps of the first semiconductor chip through, in sequence, the second metal pad, a bridging metal interconnect of the first interconnection bridge and the first metal pad, and wherein the first one of the plurality of fifth metal bumps of the second memory module couples to the first one of the plurality of third metal bumps of the second semiconductor chip through, in sequence, the fourth metal pad, a bridging metal interconnect of the second interconnection bridge and the third metal pad;
• and
• a third polymer layer over the second interconnection scheme and having a top surface coplanar with a top surface of one of the plurality of semiconductor chips.