Active capacitive shield for programmable logic array
AssigneeSTMicroelectronics International N.V.
InventorFrancois Tailliet
Life of this patent
Estimating the term…
Abstract
In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.
Claims20
A programmable logic array circuit comprising:
- an AND plane comprising a plurality of groups of product term straps;
- an OR plane comprising a plurality of output lines;
- a first plurality of dynamically driven shield lines in the AND plane;
- and
- a second plurality of dynamically driven shield lines in the OR plane;
- wherein each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines;
- wherein each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines;
- wherein, in response to a voltage on one or more of the plurality of groups of product term straps falling from a drive voltage to zero volts, a voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to the drive voltage;
- and
- wherein, in response to a voltage on one or more of the plurality of output lines falling from the drive voltage to zero volts, a voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the drive voltage.
A method of providing capacitive shielding to a programmable logic array (PLA) circuit, the method comprising:
- positioning each of a plurality of groups of product term straps of an AND plane of the PLA circuit adjacent to only one corresponding one of a first plurality of dynamically driven shield lines;
- positioning each of a plurality of output lines of an OR plane of the PLA circuit adjacent to only one corresponding one of a second plurality of dynamically driven shield lines;
- in response to a voltage on one or more of the plurality of groups of product term straps falling from a drive voltage to zero volts, driving a voltage on one or more of the first plurality of dynamically driven shield lines from zero volts to the drive voltage;
- and
- in response to a voltage on one or more of the plurality of output lines falling from the drive voltage to zero volts, driving a voltage on one or more of the second plurality of dynamically driven shield lines from zero volts to the drive voltage.
An integrated circuit comprising:
- a first plurality of signal lines;
- and
- a first plurality of dynamically driven shield lines;
- wherein each of the first plurality of signal lines is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines;
- and
- wherein, in response to a voltage on one or more of the first plurality of signal lines falling from a drive voltage to zero volts, a voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to the drive voltage.
Dependencies are inferred from the claim text.