Sectional configuration for programmable logic devices
AssigneeQuickLogic Corporation
InventorsKet Chong Yap, Chihhung Liao
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Abstract
A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.
Claims20
A device, comprising:
- a bit line driver;
- a bit line receiver;
- and
- a bit line (BL), coupled at a first end to the BL driver and at a second end to the BL receiver, wherein the BL is coupled to:
- a corresponding sectional driver, wherein the corresponding sectional driver is configured to drive the BL when the corresponding sectional driver is activated, and
- at least one corresponding sectional configuration memory latch controlled by:
- at least one sectional word line write signal, which when asserted is configured to enable data to be written into the at least one corresponding sectional configuration memory latch when the corresponding sectional driver is activated;
- and
- a sectional word line read signal.
A device, comprising:
- a bit line (BL);
- and
- a plurality of configuration sections, each of the plurality of configuration sections comprising:
- a sectional driver coupled to the BL;
- a sectional pull-up coupled to the BL;
- and
- a sectional configuration memory coupled to the BL, to the sectional driver, and to the sectional pull-up, the sectional configuration memory being coupled to a sectional word line write (WLW) line and a sectional word line read (WLR) line.
A method, comprising:
- activating a sectional driver to enable driving of a bit line (BL) by asserting a sectional write line enable (WLEN) signal, the sectional driver being coupled to the BL;
- enabling a data writes procedure for a configuration memory by asserting a word line write (WLW) signal when the sectional driver is activated, the configuration memory being coupled to the BL,
- wherein an assertion of a word line read (WLR) signal cannot overlap with an assertion of the WLW signal;
- and
- de-asserting the sectional WLEN signal when the data writes procedure for the configuration memory has been completed.
Dependencies are inferred from the claim text.